參數(shù)資料
型號： KM416RD4C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Direct Rambus DRAM(Direct Rambus 動態(tài)RAM)
中文描述： 直接Rambus公司的DRAM（動態(tài)內(nèi)存直接Rambus公司）
文件頁數(shù)： 12/59頁
文件大?。?/td> 4654K
代理商： KM416RD4C
Page 13
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
ROW-to-ROW Packet Interaction
Figure Figure shows two packets on the ROW pins sepa-
rated by an interval t
RRDELAY
which depends upon the
packet contents. No other ROW packets are sent to banks
{Ba,Ba+1,Ba-1} between packet “a” and packet “b” unless
noted otherwise. Table Table summarizes the t
RRDELAY
values for all possible cases.
Cases RR1 through RR4 show two successive ACT
commands. In case RR1, there is no restriction since the
ACT commands are to different devices. In case RR2, the
t
RR
restriction applies to the same device with non-adjacent
banks. Cases RR3 and RR4 are illegal (as shown) since bank
Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1
is inserted, t
RRDELAY
is t
RC
(t
RAS
to the PRER command,
and t
RP
to the next ACT).
Cases RR5 through RR8 show an ACT command followed
by a PRER command. In cases RR5 and RR6, there are no
restrictions since the commands are to different devices or to
non-adjacent banks of the same device. In cases RR7 and
RR8, the t
RAS
restriction means the activated bank must wait
before it can be precharged.
Cases RR9 through RR12 show a PRER command followed
by an ACT command. In cases RR9 and RR10, there are
essentially no restrictions since the commands are to
different devices or to non-adjacent banks of the same
device. RR10a and RR10b depend upon whether a bracketed
bank (Ba+-1) is precharged or activated. In cases RR11 and
RR12, the same and adjacent banks must all wait t
RP
for the
sense amp and bank to precharge before being activated.
Figure 6 : ROW-to-ROW Packet Interaction- Timing
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
2
T
17
T
18
T
19
Transaction a: ROPa
Transaction b: ROPb
a0 = {Da,Ba,Ra}
b0= {Db,Bb,Rb}
t
RRDELAY
ROPa a0
ROPb b0
Table 10 : ROW-to-ROW Packet Interaction - Rules
Case #
ROPa
Da
Ba
Ra
ROPb
Db
Bb
Rb
t
RRDELAY
Example
RR1
ACT
Da
Ba
Ra
ACT
/= Da
xxxx
x..x
t
PACKET
Figure 11
RR2
ACT
Da
Ba
Ra
ACT
== Da
/= {Ba,Ba+1,Ba-1}
x..x
t
RR
Figure 11
RR3
ACT
Da
Ba
Ra
ACT
== Da
== {Ba+1,Ba-1}
x..x
t
RC
- illegal unless PRER to Ba/Ba+1/Ba-1
Figure 10
RR4
ACT
Da
Ba
Ra
ACT
== Da
== {Ba}
x..x
t
RC
- illegal unless PRER to Ba/Ba+1/Ba-1
Figure 10
RR5
ACT
Da
Ba
Ra
PRER
/= Da
xxxx
x..x
t
PACKET
Figure 11
RR6
ACT
Da
Ba
Ra
PRER
== Da
/= {Ba,Ba+1,Ba-1}
x..x
t
PACKET
Figure 11
RR7
ACT
Da
Ba
Ra
PRER
== Da
== { Ba+1,Ba-1}
x..x
t
RAS
- needs PRER Ba first, however
Figure 10
RR8
ACT
Da
Ba
Ra
PRER
== Da
== {Ba}
x..x
t
RAS
Figure 15
RR9
PRER
Da
Ba
Ra
ACT
/= Da
xxxx
x..x
t
PACKET
Figure 12
RR10
PRER
Da
Ba
Ra
ACT
== Da
/= {Ba,Ba+-1,Ba+-2}
x..x
t
PACKET
Figure 12
RR10a
PRER
Da
Ba
Ra
ACT
== Da
== {Ba+2}
x..x
t
PACKET
/t
RP
if Ba+1 is precharged/activated.
RR10b
PRER
Da
Ba
Ra
ACT
== Da
== {Ba-2}
x..x
t
PACKET
/t
RP
if Ba-1 is precharged/activated.
RR11
PRER
Da
Ba
Ra
ACT
== Da
== {Ba+1,Ba-1}
x..x
t
RP
Figure 10
RR12
PRER
Da
Ba
Ra
ACT
== Da
== {Ba}
x..x
t
RP
Figure 10
RR13
PRER
Da
Ba
Ra
PRER
/= Da
xxxx
x..x
t
PACKET
Figure 12
RR14
PRER
Da
Ba
Ra
PRER
== Da
/= {Ba,Ba+1,Ba-1}
x..x
t
PP
Figure 12
RR15
PRER
Da
Ba
Ra
PRER
== Da
== {Ba+1,Ba-1}
x..x
t
PP
Figure 12
RR16
PRER
Da
Ba
Ra
PRER
== Da
== Ba
x..x
t
PP
Figure 12
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