參數(shù)資料
型號(hào)： KM416RD4C
廠(chǎng)商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述： 直接Rambus公司的DRAM（動(dòng)態(tài)內(nèi)存直接Rambus公司）
文件頁(yè)數(shù)： 18/59頁(yè)
文件大?。?/td> 4654K
代理商： KM416RD4C
Page 19
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
Precharge Mechanisms
Figure Figure shows an example of precharge with the
ROWR packet mechanism. The PRER command must occur
a time t
RAS
after the ACT command, and a time t
RP
before
the next ACT command. This timing will serve as a baseline
aginst which the other precharge mechanisms can be
compared.
Figure Figure (top) shows an example of precharge with a
RDA command. A bank is activated with an ROWA packet
on the ROW pins. Then, a series of four dualocts are read
with RD commands in COLC packets on the COL pins. The
fourth of these commands is a RDA, which causes the bank
to automatically precharge when the final read has finished.
The timing of this automatic precharge is equivalent to a
PRER command in an ROWR packet on the ROW pins that
is offset a time t
OFFP
from the COLC packet with the RDA
command. The RDA command should be treated as a RD
command in a COLC packet as well as a simultaneous (but
offset) PRER command in an ROWR packet when analyzing
interactions with other packets.
Figure Figure (middle) shows an example of precharge with
a WRA command. As in the RDA example, a bank is acti-
vated with an ROWA packet on the ROW pins. Then, two
dualocts are written with WR commands in COLC packets
on the COL pins. The second of these commands is a WRA,
which causes the bank to automatically precharge when the
final write has been retired. The timing of this automatic
precharge is equivalent to a PRER command in an ROWR
packet on the ROW pins that is offset a time t
OFFP
from the
COLC packet that causes the automatic retire. The WRA
command should be treated as a WR command in a COLC
packet as well as a simultaneous (but offset) PRER command
in an ROWR packet when analyzing interactions with other
packets. Note that the automatic retire is triggered by a
COLC packet a time t
RTR
after the COLC packet with the
WR command unless the second COLC contains a RD
command to the same device. This is described in more detail
in Figure Figure.
Figure Figure (bottom) shows an example of precharge with
a PREX command in an COLX packet. A bank is activated
with an ROWA packet on the ROW pins. Then, a series of
four dualocts are read with RD commands in COLC packets
on the COL pins. The fourth of these COLC packets includes
an COLX packet with a PREC command. This causes the
bank to precharge with timing equivalent to a PRER
command in an ROWR packet on the ROW pins that is offset
a time t
OFFP
from the COLX packet with the PREX
command.
Figure 13 : Precharge via PRER Command in ROWR Packet
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
ACT a0
PRER a5
t
RAS
t
RC
a0 = {Da,Ba,Ra}
a5 = {Da,Ba}
b0 = {Da,Ba,Rb}
t
RP
ACT b0
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