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參數(shù)資料
| 型號： | KM416RD4C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Direct Rambus DRAM(Direct Rambus 動態(tài)RAM) |
| 中文描述： | 直接Rambus公司的DRAM（動態(tài)內(nèi)存直接Rambus公司） |
| 文件頁數(shù)： | 20/59頁 |
| 文件大?。?/td> | 4654K |
| 代理商： | KM416RD4C |
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Page 21
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
Read Transaction - Example
Figure Figure shows an example of a read transaction. It
begins by activating a bank with an ACT a0 command in an
ROWA packet. A time t
RCD
later a RD a1 command is
issued in a COLC packet. Note that the ACT command
includes the device, bank, and row address (abbreviated as
a0) while the RD command includes device, bank, and
column address (abbreviated as a1). A time t
CAC
after the
RD command the read data dualoct Q(a1) is returned by the
device. Note that the packets on the ROW and COL pins use
the end of the packet as a timing reference point, while the
packets on the DQA/DQB pins use the beginning of the
packet as a timing reference point.
A time t
CC
after the first COLC packet on the COL pins a
second is issued. It contains a RD a2 command. The a2
address has the same device and bank address as the a1
address (and a0 address), but a different column address. A
time t
CAC
after the second RD command a second read data
dualoct Q(a2) is returned by the device.
Next, a PRER a3 command is issued in an ROWR packet on
the ROW pins. This causes the bank to precharge so that a
different row may be activated in a subsequent transaction or
so that an adjacent bank may be activated. The a3 address
includes the same device and bank address as the a0, a1, and
a2 addresses. The PRER command must occur a time t
RAS
or more after the original ACT command (the activation
operation in any DRAM is destructive, and the contents of
the selected row must be restored from the two associated
sense amps of the bank during the t
RAS
interval). The PRER
command must also occur a time t
RDP
or more after the last
RD command. Note that the t
RDP
value shown is greater
than the t
RDP,MIN
specification in Table 22. This transaction
example reads two dualocts, but there is actually enough
time to read three dualocts before t
RDP
becomes the limiting
parameter rather than t
RAS
. If four dualocts were read, the
packet with PRER would need to shift right (be delayed) by
one t
CYCLE
(note - this case is not shown).
Finally, an ACT b0 command is issued in an ROWR packet
on the ROW pins. The second ACT command must occur a
time t
RC
or more after the first ACT command and a time t
RP
or more after the PRER command. This ensures that the
bank and its associated sense amps are precharged. This
example assumes that the second transaction has the same
device and bank address as the first transaction, but a
different row address. Transaction b may not be started until
transaction a has finished. However, transactions to other
banks or other devices may be issued during transaction a.
Figure 15 : Read Transaction Example
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
20
T
24
T
28
T
17
T
21
T
25
T
29
T
18
T
22
T
26
T
30
T
19
T
23
T
27
T
31
T
32
T
36
T
40
T
44
T
33
T
37
T
41
T
45
T
34
T
38
T
42
T
46
T
35
T
39
T
43
T
47
RD a1
ACT a0
PRER a3
RD a2
Q (a2)
t
RCD
t
CAC
t
CC
Q (a1)
ACT b0
t
RAS
t
RC
t
RP
Transaction a: RD
Transaction b: xx
a0 = {Da,Ba,Ra}
b0 = {Da,Ba,Rb}
a1 = {Da,Ba,Ca1}
a2 = {Da,Ba,Ca2}
a3 = {Da,Ba}
t
CAC
t
RDP
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