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| 型號： | KM416RD4C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Direct Rambus DRAM(Direct Rambus 動態(tài)RAM) |
| 中文描述： | 直接Rambus公司的DRAM（動態(tài)內(nèi)存直接Rambus公司） |
| 文件頁數(shù)： | 14/59頁 |
| 文件大小： | 4654K |
| 代理商： | KM416RD4C |
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Page 15
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
COL-to-COL Packet Interaction
Figure Figure shows three arbitrary packets on the COL pins.
Packets “b” and “c” must be separated by an interval
t
CCDELAY
which depends upon the command and address
values in all three packets. Table Table summarizes the
t
CCDELAY
values for all possible cases.
Cases CC1 through CC5 summarize the rules for every situa-
tion other than the case when COPb is a WR command and
COPc is a RD command. In CC3, when a RD command is
followed by a WR command, a gap of t
CAC
-t
CWD
must be
inserted between the two COL packets. See Figure Figure for
more explanation of why this gap is needed. For cases CC1,
CC2, CC4, and CC5, there is no restriction (t
CCDELAY
is
t
CC
).
In cases CC6 through CC10, COPb is a WR command and
COPc is a RD command. The t
CCDELAY
value needed
between these two packets depends upon the command and
address in the packet with COPa. In particular, in case CC6
when there is WR-WR-RD command sequence directed to
the same device, a gap will be needed between the packets
with COPb and COPc. The gap will need a COLC packet
with a NOCOP command directed to any device in order to
force an automatic retire to take place. Figure 18 (right)
provides a more detailed explanation of this case.
In case CC10, there is a RD-WR-RD sequence directed to the
same device. If a prior write to the same device is unretired
when COPa is issued, then a gap will be needed between the
packets with COPb and COPc as in case CC6. The gap will
need a COLC packet with a NOCOP command directed to
any device in order to force an automatic retire to take place.
Cases CC7, CC8, and CC9 have no restriction (t
CCDELAY
is
t
CC
).
For the purposes of analyzing COL-to-ROW interactions, the
PREC, WRA, and RDA commands of the COLC packet are
equivalent to the NOCOP, WR, and RD commands. These
commands also cause a precharge operation PREC to take
place. This precharge may be converted to an equivalent
PRER command on the ROW pins using the rules summa-
rized in Figure 14.
Figure 8 : COL-to-COL Packet Interaction- Timing
CTM/CFM
DQA8..0
DQB8..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
T
17
T
18
T
19
COPa a1
Transaction a: COPa
Transaction b: COPb
Transaction c: COPc
COPc c1
a1 = {Da,Ba,Ca1}
b1 = {Db,Bb,Cb1}
c1 = {Dc,Bc,Cc1}
t
CCDELAY
COPb b1
Table 12 : COL-to-COL Packet Interaction - Rules
Case #
COPa
Da
Ba
Ca1
COPb
Db
Bb
Cb1
COPc
D
c
Bc
Cc1
t
CCDELAY
Example
CC1
xxxx
xxxxx
x..x
x..x
NOCOP
Db
Bb
Cb1
xxxx
xxxxx
x..x
x..x
t
CC
CC2
xxxx
xxxxx
x..x
x..x
RD,WR
Db
Bb
Cb1
NOCOP
xxxxx
x..x
x..x
t
CC
CC3
xxxx
xxxxx
x..x
x..x
RD
Db
Bb
Cb1
WR
xxxxx
x..x
x..x
t
CC
+t
CAC
-t
CWD
Figure 4
CC4
xxxx
xxxxx
x..x
x..x
RD
Db
Bb
Cb1
RD
xxxxx
x..x
x..x
t
CC
Figure 15
CC5
xxxx
xxxxx
x..x
x..x
WR
Db
Bb
Cb1
WR
xxxxx
x..x
x..x
t
CC
Figure 16
CC6
WR
== Db
x
x..x
WR
Db
Bb
Cb1
RD
== Db
x..x
x..x
t
RTR
Figure 17
CC7
WR
== Db
x
x..x
WR
Db
Bb
Cb1
RD
/= Db
x..x
x..x
t
CC
CC8
WR
/= Db
x
x..x
WR
Db
Bb
Cb1
RD
== Db
x..x
x..x
t
CC
CC9
NOCOP
== Db
x
x..x
WR
Db
Bb
Cb1
RD
== Db
x..x
x..x
t
CC
t
CC
or t
RTRa
CC10
RD
== Db
x
x..x
WR
Db
Bb
Cb1
RD
== Db
x..x
x..x
a.If the write buffer was full from an earlier WR command, and had not been retired when COPa=RD is executed, t
CCDELAY
will be constrained by the
t
RTR
parameter. Otherwise, the t
CC
parameter will apply.
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