參數(shù)資料
型號: KAB04D100M-TNGP
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Multi-Chip Package MEMORY
中文描述: 多芯片封裝存儲器
文件頁數(shù): 66/72頁
文件大小: 1378K
代理商: KAB04D100M-TNGP
KAB0xD100M - TxGP
Revision 1.11
August 2003
- 66 -
MCP MEMORY
SEC Only
Address
Data Out
Previous Data Valid
Data Valid
U
t
RAM TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS
U
=OE=V
IL
, ZZ=WE=V
IH
, UB or/and LB=V
IL
)
TIMING WAVEFORM OF READ CYCLE(2)
(ZZ=WE=V
IH
)
t
AA
t
RC
t
OH
(READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
3. The minimum read cycle(
t
RC
) is determined later one of the
t
RC1
and
t
RC2.
4. t
OE
(max) is met only when
OE
becomes enable after t
AA
(max).
Data Valid
High-Z
t
RC1
t
OH
t
AA
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
BHZ
t
HZ
t
RC2
t
CO
Address
CS
U
UB, LB
OE
Data out
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