參數(shù)資料
型號(hào)： KAB04D100M-TNGP
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Multi-Chip Package MEMORY
中文描述： 多芯片封裝存儲(chǔ)器
文件頁(yè)數(shù)： 46/72頁(yè)
文件大?。?/td> 1378K
代理商： KAB04D100M-TNGP
KAB0xD100M - TxGP
Revision 1.11
August 2003
- 46 -
MCP MEMORY
SEC Only
Alternate WE Controlled Write
NOTES:
1. Not 100% tested.
2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms.
Parameter
Symbol
70ns
80ns
Unit
Min
Max
Min
Max
Write Cycle Time (1)
t
WC
70
-
80
-
ns
Address Setup Time
t
AS
0
-
0
-
ns
t
ASO
55
-
55
-
ns
Address Hold Time
t
AH
45
-
45
-
ns
t
AHT
0
-
0
-
ns
Data Setup Time
t
DS
35
-
35
-
ns
Data Hold Time
t
DH
0
-
0
-
ns
Output Enable Setup Time (1)
t
OES
0
-
0
-
ns
Output Enable
Hold Time
Read (1)
t
OEH1
0
-
0
-
ns
Toggle and Data Polling (1)
t
OEH2
10
-
10
-
ns
CE
R
Setup Time
t
CS
0
-
0
-
ns
CE
R
Hold Time
t
CH
0
-
0
-
ns
Write Pulse Width
t
WP
35
-
35
-
ns
Write Pulse Width High
t
WPH
25
-
25
-
ns
Programming Operation
Word
t
PGM
14(typ.)
14(typ.)
μ
s
μ
s
μ
s
μ
s
Byte
9(typ.)
9(typ.)
Accelerated Programming Operation
Word
t
ACCPGM
9(typ.)
9(typ.)
Byte
7(typ.)
7(typ.)
Block Erase Operation (2)
t
BERS
0.7(typ.)
0.7(typ.)
sec
Vcc
R
Set Up Time
t
VCS
50
-
50
-
μ
s
Write Recovery Time from R/B
R
t
RB
0
-
0
-
ns
RESET High Time Before Read
t
RH
50
-
50
-
ns
RESET to Power Down Time
t
RPD
20
-
20
-
μ
s
Program/Erase Valid to R/B
R
Delay
t
BUSY
90
-
90
-
ns
V
ID
Rising and Falling Time
t
VID
500
-
500
-
ns
RESET Pulse Width
t
RP
500
-
500
-
ns
RESET Low to R/B
R
High
t
RRB
-
20
-
20
μ
s
RESET Setup Time for Temporary Unprotect
t
RSP
1
-
1
-
μ
s
RESET Low Setup Time
t
RSTS
500
-
500
-
ns
RESET High to Address Valid
t
RSTW
200
-
200
-
ns
Read Recovery Time Before Write
t
GHWL
0
-
0
-
ns
CE High during toggling bit polling
t
CEPH
20
-
20
-
ns
OE High during toggling bit polling
t
OEPH
20
-
20
-
ns
Write(Erase/Program)Operations
NOR Flash AC CHARACTERISTICS
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