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參數(shù)資料
| 型號(hào)： | K4H510738E |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Dual Wide Bandwidth High Output Drive Single Supply Op Amp 8-MSOP-PowerPAD -40 to 125 |
| 中文描述： | 堆疊的512Mb電子芯片DDR SDRAM內(nèi)存規(guī)格（x4/x8） |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 191K |
| 代理商： | K4H510738E |
DDR SDRAM
DDR SDRAM stacked 512Mb E-die (x4/x8)
Rev. 1.0 July. 2003
Component Notes
1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a
specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.
3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
5. For command/address input slew rate
≥
1.0 V/ns
6. For command/address input slew rate
≥
0.5 V/ns and
<
1.0 V/ns
7. For CK & CK slew rate
≥
1.0 V/ns
8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
9. Slew Rate is measured between VOH(ac) and VOL(ac).
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
11. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
12. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
13. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
Output
Test point
VSSQ
50
Figure 1 : Pullup slew rate test load
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4H510738E-TC/LA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Stacked 512Mb E-die DDR SDRAM Specification (x4/x8) |
| K4H510738E-TC/LAA | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Stacked 512Mb E-die DDR SDRAM Specification (x4/x8) |
| K4H510738E-TC/LB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Stacked 512Mb E-die DDR SDRAM Specification (x4/x8) |
| K4H510838A-TCA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H510838A-TCA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
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