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參數(shù)資料
| 型號(hào)： | K4H510738E |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Dual Wide Bandwidth High Output Drive Single Supply Op Amp 8-MSOP-PowerPAD -40 to 125 |
| 中文描述： | 堆疊的512Mb電子芯片DDR SDRAM內(nèi)存規(guī)格（x4/x8） |
| 文件頁(yè)數(shù)： | 15/22頁(yè) |
| 文件大?。?/td> | 191K |
| 代理商： | K4H510738E |
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DDR SDRAM
DDR SDRAM stacked 512Mb E-die (x4/x8)
Rev. 1.0 July. 2003
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure
proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 :
Input Slew Rate for DQ, DQS, and DM
Table 2
:
Input Setup & Hold Time Derating for Slew Rate
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
AC CHARACTERISTICS
DDR333
DDR266
DDR200
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
Units
Notes
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
TBD
TBD
TBD
TBD
0.5
4.0
V/ns
a, m
Input Slew Rate
tIS
tIH
Units
Notes
0.5 V/ns
0
0
ps
i
0.4 V/ns
+50
0
ps
i
0.3 V/ns
+100
0
ps
i
Input Slew Rate
tDS
tDH
Units
Notes
0.5 V/ns
0
0
ps
k
0.4 V/ns
+75
+75
ps
k
0.3 V/ns
+150
+150
ps
k
Parameter
Symbol
AA
(DDR266@CL=2.0)
Min
A2
(DDR266@CL=2.0)
Min
B0
(DDR266@CL=2.5))
Min
Unit
Note
Max
Max
Max
Mode register set cycle time
tMRD
15
15
15
ns
DQ & DM setup time to DQS
tDS
0.5
0.5
0.5
ns
j, k
DQ & DM hold time to DQS
tDH
0.5
0.5
0.5
ns
j, k
Control & Address input pulse width
tIPW
2.2
2.2
2.2
ns
8
DQ & DM input pulse width
tDIPW
1.75
1.75
1.75
ns
8
Power down exit time
tPDEX
7.5
7.5
7.5
ns
Exit self refresh to non-Read command
tXSNR
75
75
75
ns
Exit self refresh to read command
tXSRD
200
200
200
tCK
Refresh interval time
tREFI
7.8
7.8
7.8
us
4
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
11
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
10, 11
Data hold skew factor
tQHS
0.75
0.75
0.75
ns
11
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
2
Active to Read with Auto precharge
command
tRAP
20
20
20
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
13
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相關(guān)代理商/技術(shù)參數(shù) |
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| K4H510738E-TC/LA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Stacked 512Mb E-die DDR SDRAM Specification (x4/x8) |
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| K4H510838A-TCA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
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