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參數(shù)資料
| 型號： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級I / O）的初步規(guī)范V0.5 |
| 文件頁數(shù)： | 97/128頁 |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
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IT8673F
7
line is printed.
Bit 0 STB: Inverse of the STB# pin, this pin controls the data strobe signal to the printer.
(4) EPP Address Port (Primary Base Address + 03h)
The EPP Address Port is only available in the EPP mode. When the Host writes to this port, the contents of
D0 -D7 are buffered and output to PD0 - PD7. The leading edge of IOW causes an EPP ADDRESS WRITE
cycle. When the Host reads from this port, the contents of PD0 - PD7 are read. The leading edge of IOR
causes an EPP ADDRESS READ cycle.
(5) EPP Data Ports 0-3 (Primary Base Address + 04h - 07h)
The EPP Data Ports are only available in the EPP mode. When the Host writes to these ports, the contents
of D0 - D7 are buffered and output to PD0 - PD7. The leading edge of IOW causes an EPP DATA WRITE
cycles. When the Host reads from these ports, the contents of PD0 - PD7 are read. The leading edge of IOR
causes an EPP DATA READ cycle.
11.6.2 EPP Operation
When the parallel port of the IT8673F is selected to be in the EPP mode, the SPP mode is also available.
Address/Data Port address is decoded (Base address + 03h- 07h), the PD bus is in the SPP mode, and the
output signals such as STB#, AFD#, INIT#, and SLIN# are set by SPP control port. The direction of the data
port is controlled by the bit 5 of the control port register. A 10-msec time is required to prevent the system
from lockup. The time has elapsed from the beginning of the IOCHRDY high (EPP READ/WRITE cycle) to
WAIT# being deasserted. If a time-out occurs, the current EPP READ/WRITE cycle is aborted and a logic
"1" will be read in the bit 0 of the status port register. The Host must write 0 to bits 0, 1, 3 of the control port
register before any EPP READ/WRITE cycle (EPP spec.) The pins STB#, AFD# and SLIN# are controlled
by hardware for the hardware handshaking during EPP READ/WRITE cycle.
(1) EPP ADDRESS WRITE
1. The Host writes a byte to the EPP Address Port (Base address + 03h). The chip drives D0 - D7 onto PD0
- PD7.
2. The chip drives IOCHRDY low and asserts WRITE (STB#) and ASTB# (SLIN#) after IOW is active.
3. Peripheral deasserts WAIT#, indicating that the chip may begin the termination of this cycle. The chip
then deasserts ASTB#, latches the address from D0 - D7 to PD bus and releases IOCHRDY, allowing
the Host to complete the I/O WRITE cycle.
4. Peripheral asserts WAIT#, indicating that it acknowledges the termination of the cycle. The chip then
deasserts WRITE to terminate the cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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