
IT8673F
2
(12) Configuration Register B (cnfgB) (Secondary Base+1h, Mode 111)
This register is
read only
.
cnfgB(7): A logic “0” read indicates that the chip does not support hardware RLE compression.
cnfgB(6):Returns the value on the ISA IRQ line to warn possible conflicts.
cnfgB(5)-cnfgB(3): A value 000 read indicates that the interrupt must be selected with jumpers.
cnfgB(2)-cnfgB(0): A value 000 read indicates that the DMA channel is a jumpered 8-bit DMA.
(13) Extended Control Register (ECR) (Secondary Base+2h, Mode All)
Table 11-43. Extended Control Register (ECR) Mode and Description
ECR
Mode and Description
000
Standard Parallel Port Mode. The FIFO is reset and the direction bit dcr(5) is always “0” (forward direction) in
this mode.
001
PS/2 Parallel Port Mode. It is similar to the SPP mode except that the dcr(5) is
read/write
. When dcr(5) is “1”,
the PD bus is tri-state. Reading the data port returns the value on the PD bus instead of the value of the data
register.
010
Parallel Port Data FIFO Mode. This mode is similar to the 000 mode, except that the Host writes or DMA
transfers the data bytes to the FIFO. The FIFO data is then automatically sent to the peripheral using the
standard parallel port protocol. This mode is only valid in the forward direction (dcr(5)=0)
011
ECP Parallel Port Mode. In the forward direction, bytes placed into the ecpDFifo and ecpAFifo are stored in a
single FIFO and automatically sent to the peripheral under the ECP protocol. In the reverse direction, bytes
are sent to the ecpDFifo from ECP port.
100, 101 Reserved, not defined.
110
Test mode. In this mode, the FIFO may be read from or written to, but it cannot be sent to the peripheral.
111
Configuration mode. In this mode, the cnfgA and cnfgB registers are accessible at 0x400 and 0x401.