參數(shù)資料
型號: IT8673F
廠商: Electronic Theatre Controls, Inc.
英文描述: GT 35C 35#12 SKT PLUG
中文描述: 先進(jìn)的輸入/輸出(高級I / O)的初步規(guī)范V0.5
文件頁數(shù): 51/128頁
文件大?。?/td> 780K
代理商: IT8673F
IT8673F
11. Functional Description
11.1 General Purpose I/O
IT8673F provides flexible I/O control and special functions for the system designers through a set of
General Purpose I/O pins (GPIO). Some of GPIO pins are multi-functional. The GPIO functions will not be
performed unless the related enable bits of the GPIO Multi-function Pin Selection register (Index 25h of
Global Configuration Register) are set. GPIO function includes the simple I/O function and alternate
function, and the function selection is determined by Simple I/O Enable Register (Index=F5h).
The Simple I/O function includes a set of registers, which correspond to the GPIO pins. The accessed I/O
ports are programmable. Base Address is programmed on the GPIO Simple I/O Base Address LSB and
MSB registers (LDN=07h, Index=66h and 67h).
The Alternate Function provides several special functions for users, including three chip select strobes
(CS0, CS1, CS2), SMI# output routing, Interrupt steering, Panel Button De-bounce, Keyboard Lock input
routing, LED Blinking, PCI CLKRUN# routing, and RING routing (sub-function of APC). All these functions
can be programmed to all GPIO pins, except the RING# function.
The GP set selection register (Index=F0h) is used to determine the set X of the some registers (Index=F1h
and F2h). Before these registers can be programmed, this register (Index=F0h) must be determined in first.
IT8673F provides flexible control registers related to each of three chip select strobes. Each chip select
strobe can be programmed as 1, 2, 4 or 8 via consecutive I/O ports decoding. Each chip select strobe can
also be programmed to qualify with IOR# or IOW# strobe. There are four types of qualifying conditions: pure
address decided, asserted on address matching and IOR# asserted, asserted on address matching and
IOW# asserted, asserted on address matching and IOR# or IOW# asserted.
The Key Lock function locks the keyboard to invalidate any key stroke. The programming method is to set
bit 2 on the KBC (keyboard) Special Configuration Register (Index=F0h, LDN=05h). The Keyboard Lock
Pin Mapping Register (Index=F9h) must also be programmed correctly.
The Interrupt steering function provides a useful feature for motherboard designers. Through this mapping
method, the interrupt of other on-board devices can be easily modified by programming the registers of
Index = 70h, 71h, 72h, and 73h.
The Blinking function provides a low frequency blink output. By connecting to some external components, it
can be used to control a power LED. There are several frequencies that can be selected.
The PCI CLKRUN# output is used to resume the PCI CLOCK in system power down mode, when the
IT8673F devices (Serial Port 1, Serial Port 2, Parallel Port…) request to generate an interrupt through SIRQ
protocol. All the devices will not be resumed unless the related enable bits in SMI# control register 1 and 2
are set.
The SMI# is a non-maskable interrupt dedicated for transparent power management. It consists of different
enable interrupts from each of the functional blocks in IT8673F. The interrupts are enabled onto the SMI#
output via the SMI# control register 1 and SMI# control register 2. The SMI# status registers 1 and 2 are
used to read the status of the SMI input events. All the SMI# status register bits can be cleared when the
corresponding sources events become invalidated. These bits can also be cleared by writing 1 to bit 7 of
SMI# control register 2, whether the events of the corresponding sources are invalidated or not. The SMI#
can be programmed as pulse mode or level mode whenever an SMI# event occurs. The logic equation of
the SMI# event is described below:
SMI# event = (EN_FIRQ and FIRQ) or (EN_S1IRQ and S1IRQ) or (EN_S2IRQ and S2IRQ) or (EN_PIRQ
and PIRQ) or (EN_KBC(Keyboard) and KIRQ) or (EN_KBC(Mouse) and MIRQ) or (EN_GPIRQ1 and
GPIRQ1) or (EN_GPIRQ2 or GPIRQ2).
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