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參數(shù)資料
| 型號(hào)： | IT8673F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 先進(jìn)的輸入/輸出（高級(jí)I / O）的初步規(guī)范V0.5 |
| 文件頁(yè)數(shù)： | 58/128頁(yè) |
| 文件大?。?/td> | 780K |
| 代理商： | IT8673F |
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IT8673F
11.4.3 Hardware Reset (RESET Pin)
When the FDC receives a RESET signal, all registers of the FDC core are cleared (except those
programmed by the SPECIFY command). To exit the reset state, the host must clear the DOR bit.
8
48
11.4.4 Software Reset (DOR Reset and DSR Reset)
When the reset bit in the DOR or the DSR is set, all registers of the FDC core are cleared. A reset
performed by setting the reset bit in the DOR has higher priority over a reset performed by setting the reset
bit in the DSR. In addition, to exit the reset state, the DSR bit is self-clearing, while the host must clear the
DOR bit.
11.4.5 Digital Data Separator
The internal digital data separator is comprised of a digital PLL and associated support circuitry. It is
responsible for synchronizing the raw data signal read from the floppy disk drive. The synchronized signal is
used to separate the encoded clock from the data pulses.
11.4.6 Write Precompensation
Write precompensation is a method that can be used to adjust the effects of bit shift on data as it is written
to the disk. It is harder for the data separator to read data that has been subject to bit shifting. Soft read
errors can occur due to such bit shifting. Write precompensation predicts where the bit shifting might occur
within a data pattern and shifts the individual data bits back to their nominal positions. The FDC permits the
selection of write precompensation via the Data Rate Select Register (DSR) bits 2 through 4.
11.4.7 Data Rate Selection
Selecting one of the four possible data rates for the attached floppy disks is accomplished by setting the
Diskette Control Register (DCR) or Data Rate Select Register (DSR) bits to 0 and 1. The data rate is
determined by the last value that is written to either the DCR or the DSR. When the data rate is set, the data
separator clock is scaled appropriately.
11.4.8 Status, Data and Control Registers
11.4.8.1 Digital Output Register (DOR, FDC Base Address + 02h)
This is a Read/Write register. It controls drive selection and motor enables as well as a software reset bit
and DMA enable. The I/O interface reset may be used at any time to clear the DOR’s contents.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IT8687R | 制造商:ITE 功能描述: |
| IT86B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
| IT86G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|600V V(DRM)|8A I(T)RMS|TO-220 |
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