
IT8673F
106
Table 11-49. Receiver Demodulation High Frequency (HCFS = 1)
RXDCR
CFQ
001
010
011
100
101
110
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. (Hz)
00011
375
425
350
450
325
475
300
500
275
525
250
550 400k
01000
421.9 478.1 393.8 506.3 365.6 534.4 337.5 562.5 309.4 590.6 281.3 618.8 450k
01011
450
510
420
540
390
570
360
600
330
630
300
660
480k
01011
468.8 531.3 437.5 562.5 406.3 593.8
375
625 343.8 656.3 312.5 687.5 500k
11.8.6.6 CIR Baud Rate Divisor Low Byte Register (BDLR)
The BDLR, an 8-bit
read/write
register, is used to program the CIR Baud Rate clock.
Address: Base address + 5h (when BR = 1)
Bit
7-0
R/W
Default
00h
Description
R/W
Baud Rate Divisor Low Byte (BDLR[7:0])
These bits are the low byte of the register used to divide the Baud Rate clock.
11.8.6.7 CIR Baud Rate Divisor High Byte Register (BDHR)
The BDHR, an 8-bit
read/write
register, is used to program the CIR Baud Rate clock.
Address: Base address + 6h (when BR = 1)
Bit
7-0
R/W
Default
00h
Description
R/W
Baud Rate Divisor High Byte (BDHR[7:0])
These bits are the high byte of the register used to divide the Baud Rate clock.
Baud rate divisor = 115200 / baud rate
Ex1: 2400bps
115200 /2400 = 48
48(d) = 0030 (h)
BDHR = 00(h), BDLR = 30(h)
Ex2: bit width = 0.565 ms
1770 bps
115200 / 1770 = 65(d) = 0041(h)
BDHR = 00(h), BDLR = 0041(h)
11.8.6.8 CIR Transmitter Status Register (TSR)
The TSR, an 8-bit
read only
register, provides the Transmitter FIFO status.
Address: Base address + 5h
Bit
R/W
Default
Description
7-6
R
-
Reserved
5-0
R
000000b
Transmitter FIFO Byte Count (TXFBC[5:0])
Return the number of bytes left in the Transmitter FIFO.