參數(shù)資料
型號(hào): ISPCLOCK5600
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
中文描述: 在系統(tǒng)可編程,零延遲時(shí)鐘發(fā)生器通用扇出緩沖器
文件頁(yè)數(shù): 8/47頁(yè)
文件大小: 871K
代理商: ISPCLOCK5600
Lattice Semiconductor
ispClock5600 Family Data Sheet
8
Output Test Loads
Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other
selected parameters as noted in the various tables of this data sheet.
Figure 3. CMOS Termination Load
Figure 4. HSTL/SSTL Termination Load
Figure 5. LVDS/LVPECL Termination Load
ispCLOCK
SCOPE
950
50
/3"
50
/36"
50
5pF
Zo = 50
ispCLOCK
SCOPE
50
/3"
50
/36"
950
50
5pF
Zo = HSTL: ~20
SSTL: 40
VTERM
50
ispCLOCK
50
/36"
34
34
50
/36"
0.1U
0.1U
44.2
3pF
(parasitic)
3pF
(parasitic)
SCOPE
50
50
5pF
5pF
ChA
ChB
50
/3"
50
/1"
50
/3"
50
/1"
Interface Circuit
33.2
33.2
相關(guān)PDF資料
PDF描述
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ISPPAC-CLK5620V-01T48C LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm
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