參數(shù)資料
型號(hào): ISPCLOCK5600
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
中文描述: 在系統(tǒng)可編程,零延遲時(shí)鐘發(fā)生器通用扇出緩沖器
文件頁(yè)數(shù): 42/47頁(yè)
文件大?。?/td> 871K
代理商: ISPCLOCK5600
Lattice Semiconductor
ispClock5600 Family Data Sheet
42
GOE
– Global output enable. This pin drives all outputs to a high-impedance state when it is pulled HIGH. GOE
also controls the internal feedback buffer, so that bringing GOE high will cause the PLL to lose lock.
PS0, PS1
– These input pins are used to select one of four user-de
fi
ned con
fi
guration pro
fi
les for the device.
PLL_BYPASS
– When this pin is pulled LOW, the V-dividers are driven from the output of the device’s VCO, and
the device behaves as a phase-locked loop. When this pin is pulled HIGH, the V-dividers are driven directly from
the output of the M-divider, and the PLL functions are effectively bypassed.
RESET
– When this pin is pulled HIGH, all on-board counters are reset, and lock is lost.
TEST1,TEST2
– These pins are used for factory test functions, and should always be tied to ground.
n/c
– These pins have no internal connection. We recommend that they be left unconnected.
RESERVED
– These pins are reserved for factory use and should be left unconnected.
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5610V-01T100C In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
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ISPPAC-CLK5620V-01T100I In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
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ISPPAC-CLK5620V-01T48C LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm
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