參數(shù)資料
型號: ISPCLOCK5600
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
中文描述: 在系統(tǒng)可編程,零延遲時鐘發(fā)生器通用扇出緩沖器
文件頁數(shù): 30/47頁
文件大?。?/td> 871K
代理商: ISPCLOCK5600
Lattice Semiconductor
ispClock5600 Family Data Sheet
30
Figure 26. Output Timing Adders for Logic Type (a) and Output Slew Rate (b)
Similarly, when one changes the slew rate of an output, the output slew rate adders (t
IOS
) can be used to predict
the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are
measured. For example, in the case of outputs con
fi
gured to the same logic type (e.g. LVCMOS 1.8V), if one output
is set to the fastest slew rate (1, t
IOS
= 0ps), and another set to slew rate 3 (t
IOS
= 660ps), then one could expect
660ps of skew between the two outputs, as shown in Figure 26b.
Static Phase Offset and Input-Output Skew
The ispClock5600’s external feedback inputs can be used to obtain near-zero effective delays from the clock refer-
ence input pins to a designated output pin. In external feedback mode (Figure 27) the PLL will attempt to force the
output phase so that the rising edge phase (t
φ
) at the feedback input matches the rising edge phase at the refer-
ence input. The residual error between the two is speci
fi
ed as the static phase error. Note that any propagation
delays (t
FBK
) in the external feedback path drive the phase of the output signal
backwards
in time as measured at
the output. For this reason, if zero input-to-output delays are required in external feedback mode, the length of the
signal path between the output pin and the feedback pin should be minimized.
Figure 27. External Feedback Mode and Timing Relationships
Other Features
Internal Feedback Mode
In addition to supporting the use of external feedback to close the phase-locked loop, ispClock5620 also provides
the option of using an internal feedback path for this function. This feature is useful for minimizing external connec-
tions and routing in situations where one does not wish to attempt to compensate for external signal path delays.
LVPECL Output
(T
IOS
= 0)
LVTTL Output
(T
IOS
= 0.1ns)
0.15ns
(a)
LVCMOS Output
(Slew rate=1)
LVCMOS Output
(Slew rate=3)
660ps
(b)
Input Reference Clock
REF
FBK
BANK
OUTPUT
ispClock5600
Delay = t
FBK
t
φ
t
FBK
REF
FBK
BANK
OUTPUT
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