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參數(shù)資料
| 型號： | ISPCLOCK5600 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數(shù)： | 23/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPCLOCK5600 |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
23
In the case where an output bank is unused, the associated VCCO pin may be either left
fl
oating or tied to ground
to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground
where possible. All GND0 pins must be tied to ground, regardless of whether or not the associated bank is used.
Figure 19. ispClock5600 Output Driver and Skew Control
Each of the ispClock5600’s output driver banks can be con
fi
gured to support the following logic outputs:
LVTTL
LVCMOS (1.8V, 2.5V, 3.3V)
SSTL2
SSTL3
HSTL
LVDS
Differential LVPECL (3.3V)
To provide LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL outputs, the CMOS output drivers in each bank are
enabled. These circuits provide logic outputs which swing from ground to the VCCO supply rail. The choice of
VCCO to be supplied to a given bank is determined by the logic standard to which that bank is con
fi
gured. Because
each pair of outputs has its own VCCO supply pin, each bank can be independently con
fi
gured to support a differ-
ent logic standard. Note that the two outputs associated with a bank must necessarily be con
fi
gured to the same
logic standard. The source impedance of each of the two outputs in each bank may be independently set over a
range of 40
to 70
in 5
steps. A low impedance option (
≈
20
) is also provided for cases where low source ter-
mination is desired on a given output.
Control of output slew rate is also provided in LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL output modes. Four
output slew-rate settings are provided, as speci
fi
ed in the “Output Rise Times” and “Output Fall Times” tables in this
data sheet.
To provide LVDS and differential LVPECL outputs, a separate internal driver is used which provides the correct
LVDS or LVPECL logic levels when operating from a 3.3V VCCO. Because both LVDS and differential LVPECL
transmission lines are normally terminated with a single 100
resistor between the ‘+’ and ‘-’ signal lines at the far
OE
Control
From V-Dividers
Skew
Adjust
Skew
Adjust
BANKxA
BANKxB
Single-ended
‘A’ output Driver
Single-ended
‘B’ output Driver
Differential
(PECL/LVDS)
Driver
OE
Control
OE
Control
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T48C | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPCLOCK5600A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPCLOCK5610A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPCLOCK5620A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPD60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DARLINGTON-NPN-OUTPUT DC-INPUT OPTOCOUPLER |
| ISPD60_10 | 制造商:ISOCOM 制造商全稱:ISOCOM 功能描述:NON BASE LEAD OPTICALLY COUPLED ISOLATOR PHOTODARLINGTON OUTPUT |
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