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參數(shù)資料
| 型號： | ISPCLOCK5600 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| 中文描述： | 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數(shù)： | 20/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPCLOCK5600 |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
20
Figure 14. LVCMOS/LVTTL Input Receiver Configuration
HSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input
pair. The ‘-’ input terminal should be tied to the appropriate V
REF
value, and the associated REFVTT or FBKVTT
terminal should be tied to a V
TT
termination supply. The positive input’s terminating resistor should be engaged and
set to 50
. Figure 15 shows an appropriate con
fi
guration. Refer to the “Recommended Operating Conditions -
Supported Logic Standards” table in this data sheet for suitable values of V
REF
and V
TT.
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing
fl
uctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator speci
fi
cally designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 15. SSTL2, SSTL3, HSTL Receiver Configuration
R
T
OPEN
REFA-
REFA+
REFVTT
Single-ended
Receiver
No Connect
No Connect
Signal In
ispClock5600
50
CLOSED
REFA-
REFA+
REFVTT
VTT
Differential
Receiver
VREF IN
Signal In
ispClock5600
OPEN
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PDF描述 |
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| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T48C | LED Area Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:525nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPCLOCK5600A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPCLOCK5610A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPCLOCK5620A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPD60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DARLINGTON-NPN-OUTPUT DC-INPUT OPTOCOUPLER |
| ISPD60_10 | 制造商:ISOCOM 制造商全稱:ISOCOM 功能描述:NON BASE LEAD OPTICALLY COUPLED ISOLATOR PHOTODARLINGTON OUTPUT |
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