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參數(shù)資料
| 型號： | ISL12025 |
| 廠商： | Intersil Corporation |
| 英文描述： | Real-Time Clock/Calendar with EEPROM(EEPROM實(shí)時(shí)時(shí)鐘/日歷) |
| 中文描述： | 實(shí)時(shí)時(shí)鐘/日歷（EEPROM的實(shí)時(shí)時(shí)鐘/日歷帶有EEPROM） |
| 文件頁數(shù)： | 5/27頁 |
| 文件大?。?/td> | 412K |
| 代理商： | ISL12025 |
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5
FN6371.2
October 19, 2007
t
LOW
Clock LOW Time
Measured at the 30% of V
DD
crossing.
1300
ns
t
HIGH
Clock HIGH Time
Measured at the 70% of V
DD
crossing.
600
ns
t
SU:STA
START Condition Set-up Time
SCL rising edge to SDA falling
edge. Both crossing 70% of V
DD
.
600
ns
t
HD:STA
START Condition Hold Time
From SDA falling edge crossing
30% of V
DD
to SCL falling edge
crossing 70% of V
DD
.
600
ns
t
SU:DAT
Input Data Set-up Time
From SDA exiting the 30% to 70%
of V
DD
window, to SCL rising edge
crossing 30% of V
DD
.
100
ns
t
HD:DAT
Input Data Hold Time
From SCL falling edge crossing
70% of V
DD
to SDA entering the
30% to 70% of V
DD
window.
0
ns
t
SU:STO
STOP Condition Set-up Time
From SCL rising edge crossing
70% of V
DD
, to SDA rising edge
crossing 30% of V
DD
.
600
ns
t
HD:STO
STOP Condition Hold Time for
Read or Volatile Only Write
From SDA rising edge to SCL
falling edge. Both crossing 70% of
V
DD
.
600
ns
t
DH
Output Data Hold Time
From SCL falling edge crossing
30% of V
DD
, until SDA enters the
30% to 70% of V
DD
window.
0
ns
Cpin
SDA and SCL Pin Capacitance
10
pF
t
WC
Non-Volatile Write Cycle Time
12
20
ms
10
t
R
SDA and SCL Rise Time
From 30% to 70% of V
DD
20 +
0.1 x Cb
250
ns
11
t
F
SDA and SCL Fall Time
From 70% to 30% of V
DD
20 +
0.1 x Cb
250
ns
11
Cb
Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
11
R
PU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and
t
F
.
For Cb = 400pF, max is about
2k
Ω
~2.5k
Ω
.
For Cb = 40pF, max is about
15k
Ω
~20k
Ω
1
k
Ω
11
NOTES:
3. RESET Inactive (no reset).
4. V
IL
= V
DD
x 0.1, V
IH
= V
DD
x 0.9, f
SCL
= 400kHz.
5. V
RESET
= 2.63V (VDD must be greater than V
RESET
), V
BAT
= 0V.
6. Bit BSW = 0 (Standard Mode), V
BAT
≥
1.8V.
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
9. Parameter is not 100% tested.
10. t
WC
is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
11. These are I
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
Serial Interface (I
2
C) Specifications
(Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ISL12025
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| ISL12025IBZ | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK/CLNDR W/EEPROM 2 63VSET RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12025IBZ-T | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK/CLNDR W/EEPROM 2 63VSET RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12025IVZ | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK/CLNDR W/EEPROM 2 63SET 8 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12025IVZ-T | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK/CLNDR W/EEPROM 2 63SET 8 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12026 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock/Calendar with I2C Bus? and EEPROM |
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