參數(shù)資料
型號: ISL12025
廠商: Intersil Corporation
英文描述: Real-Time Clock/Calendar with EEPROM(EEPROM實時時鐘/日歷)
中文描述: 實時時鐘/日歷(EEPROM的實時時鐘/日歷帶有EEPROM)
文件頁數(shù): 25/27頁
文件大?。?/td> 412K
代理商: ISL12025
25
FN6371.2
October 19, 2007
Alarm Operation Examples
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm 0 set with single interrupt (IM = “0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm0 registers as follows:
B. Also, the AL0E bit must be set as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds change from 59 to 00) by setting the AL0 bit in the
status register to “1”.
EXAMPLE 2
Pulsed interrupt once per minute (IM = “1”)
Interrupts at one minute intervals when the seconds register
is at 30s.
A. Set Alarm0 registers as follows:
B. Set the Interrupt register as follows:
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
ALARM0
REGISTER
BIT
DESCRIPTION
7
6
5
4
3
2
1
0
HEX
SCA0
0
0
0
0
0
0
0
0
00h
Seconds disabled
MNA0
1
0
1
1
0
0
0
0
B0h
Minutes set to 30,
enabled
HRA0
1
0
0
1
0
0
0
1
91h
Hours set to 11,
enabled
DTA0
1
0
0
0
0
0
0
1
81h
Date set to 1,
enabled
MOA0
1
0
0
0
0
0
0
1
81h
Month set to 1,
enabled
DWA0
0
0
0
0
0
0
0
0
00h
Day of week
disabled
CONTROL
REGISTER
BIT
DESCRIPTION
7
6
5
4
3
2
1
0
HEX
INT
0
0
1
0
0
0
0
0
x0h
Enable Alarm
ALARM0
REGISTER
BIT
DESCRIPTION
7 6 5 4 3 2 1 0 HEX
SCA0
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
enabled
MNA0
0 0 0 0 0 0 0 0
00h Minutes disabled
HRA0
0 0 0 0 0 0 0 0
00h Hours disabled
DTA0
0 0 0 0 0 0 0 0
00h Date disabled
MOA0
0 0 0 0 0 0 0 0
00h Month disabled
DWA0
0 0 0 0 0 0 0 0
00h Day of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION
7 6 5 4 3 2 1 0 HEX
INT
1 0 1 0 0 0 0 0
x0h Enable Alarm and Int
Mode
ISL12025
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