參數(shù)資料
型號(hào)： ISL12025
廠商： Intersil Corporation
英文描述： Real-Time Clock/Calendar with EEPROM(EEPROM實(shí)時(shí)時(shí)鐘/日歷)
中文描述： 實(shí)時(shí)時(shí)鐘/日歷（EEPROM的實(shí)時(shí)時(shí)鐘/日歷帶有EEPROM）
文件頁數(shù)： 12/27頁
文件大?。?/td> 412K
代理商： ISL12025
12
FN6371.2
October 19, 2007
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See “Device Operation” on page 13
and “Application Section” on page 21 for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described under this section
are non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
Oscillator Compensation Registers
There are two trimming options.
- ATR. Analog Trimming Register
- DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64ppm to +110ppm of
total adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation.
The effective on-chip series load capacitance, C
LOAD
,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C
LOAD
is changed via two digitally
controlled capacitors, C
X1
and C
X2
, connected from the X1
and X2 pins to ground (see Figure 12). The value of C
X1
and
C
X2
is given by Equation 1:
The effective series load capacitance is the combination of
C
X1
and C
X2
:
For example:
C
LOAD
(ATR = 00000) = 12.5pF,
C
LOAD
(ATR = 100000) = 4.5pF, and
C
LOAD
(ATR = 011111) = 20.25pF.
The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit, where:
DTR2 = 0 means frequency compensation is >0.
DTR2 = 1 means frequency compensation is <0.
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
TABLE 3.
B
B
B
PROTECTED ADDRESSES
ISL12025
ARRAY LOCK
0
0
0
None (Default)
None
0
0
1
180
h
– 1FF
h
Upper 1/4
0
1
0
100
h
– 1FF
h
Upper 1/2
0
1
1
000
h
– 1FF
h
Full Array
1
0
0
000
h
– 03F
h
First 4 Pages
1
0
1
000
h
– 07F
h
First 8 Pages
1
1
0
000
h
– 0FF
h
First 16 Pages
1
1
1
000
h
– 1FF
h
Full Array
FIGURE 12. DIAGRAM OF ATR
C
X1
X1
X2
CRYSTAL
OSCILLATOR
C
X2
CX
16 b5
8 b4
4 b3
2 b2
1 b1
0.5 b0
9
+
+
+
+
+
+
(
)
pF
=
(EQ. 1)
CLOAD
X1
----------
X2
----------
+
----------------------------------
=
CLOAD
-----------------------------------------------------------------------------------------------------------------------------
9
+
pF
=
(EQ. 2)
ISL12025
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