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參數(shù)資料
| 型號： | ISL12025 |
| 廠商： | Intersil Corporation |
| 英文描述： | Real-Time Clock/Calendar with EEPROM(EEPROM實時時鐘/日歷) |
| 中文描述： | 實時時鐘/日歷（EEPROM的實時時鐘/日歷帶有EEPROM） |
| 文件頁數(shù)： | 13/27頁 |
| 文件大小： | 412K |
| 代理商： | ISL12025 |
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13
FN6371.2
October 19, 2007
A range from -30ppm to +30ppm can be represented by
using the three bits previously explained.
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: Serial Bus Interface (Enable)
The serial bus can be disabled in Battery Backup Mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in Battery
Backup Mode by setting this bit to “0” (default is “0”). See
“Power Control Operation” on page 14.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between V
DD
and Back Up Battery. There are two
options:
Option 1. Standard: Set “BSW = 0”
Option 2. Legacy /Default Mode: Set “BSW = 1”
See “Power Control Operation” on page 14 for more details.
Also see “I
2
C Communications During Battery Backup and
LVR Operation” on page 23 for important details.
VTS2, VTS1, VTS0: V
RESET
Select Bits
The ISL12025 is shipped with a default V
DD
threshold
(V
RESET
) per the “Ordering Information” table on page 1.
This register is a non-volatile with no protection, therefore
any writes to this location can change the default value from
that marked on the package. If not changed with a non-
volatile write, this value will not change over normal
operating and storage conditions. However, ISL12025 has
four (4) additional selectable levels to fit the customers
application. Levels are: 4.64V (default), 4.38V, 3.09V, 2.92V
and 2.63V. The V
RESET
selection is via 3 bits (VTS2, VTS1
and VTS0). See Table
5.
Care should be taken when changing the V
RESET
select
bits. If the V
RESET
voltage selected is higher than V
DD
, then
the device will go into RESET and unless V
DD
is increased,
the device will no longer be able to communicate using the
I
2
C bus.
Unique ID Registers
There are eight register bytes for storing the device ID.
(Address 0020h to 0027h). Each device contains these
bytes to provide a unique 64-bit ID programmed and tested
in the factory before shipment. These registers are read-
only, intended for serialization of end equipment, and cannot
be changed or overwritten.
Device Operation
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers
requires the following steps:
1. Write a 02h to the Status Register to set the Write Enable
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a start and
ended with a stop).
2. Write a 06h to the Status Register to set both the Register
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required.
(Operation proceeded by a start and ended with a stop).
Write all eight bytes to the RTC registers, or one byte to the
SR, or one to five bytes to the control registers. This
sequence starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is terminated
by a stop bit. A write to the EEPROM registers in the CCR
will initiate a non-volatile write cycle and will take up to 20ms
to complete. A write to the RTC registers (SRAM) will require
much shorter cycle time (t = t
BUF
). Writes to undefined areas
have no effect. The RWEL bit is reset by the completion of a
write to the CCR, so the sequence must be repeated to
again initiate another change to the CCR contents. If the
sequence is not completed for any reason (by sending an
incorrect number of bits or sending a start instead of a stop,
for example) the RWEL bit is not reset and the device
remains in an active mode. Writing all zeros to the status
register resets both the WEL and RWEL bits. A read
operation occurring between any of the previous operations
will not interrupt the register write operation.
Alarm Operation
Since the alarm works as a comparison between the alarm
registers and the RTC registers, it is ideal for notifying a host
processor of a particular time event and trigger some action
as a result. The host can be notified by polling the Status
Register (SR) Alarm bits. These two volatile bits (AL1 for
TABLE 4. DIGITAL TRIMMING REGISTERS
DTR REGISTER
ESTIMATED FREQUENCY
PPM
DTR2
DTR1
DTR0
0
0
0
0
0
1
0
+10
0
0
1
+20
0
1
1
+30
1
0
0
0
1
1
0
-10
1
0
1
-20
1
1
1
-30
TABLE 5.
VTS2
VTS1
VTS0
V
RESET
0
0
0
4.64V
0
0
1
4.38V
0
1
0
3.09V
0
1
1
2.92V
1
0
0
2.63V
ISL12025
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL12025IBZ | 功能描述:實時時鐘 REAL TIME CLK/CLNDR W/EEPROM 2 63VSET RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12025IBZ-T | 功能描述:實時時鐘 REAL TIME CLK/CLNDR W/EEPROM 2 63VSET RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12025IVZ | 功能描述:實時時鐘 REAL TIME CLK/CLNDR W/EEPROM 2 63SET 8 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12025IVZ-T | 功能描述:實時時鐘 REAL TIME CLK/CLNDR W/EEPROM 2 63SET 8 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12026 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock/Calendar with I2C Bus? and EEPROM |
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