參數(shù)資料
型號(hào)： ISL12025
廠(chǎng)商： Intersil Corporation
英文描述： Real-Time Clock/Calendar with EEPROM(EEPROM實(shí)時(shí)時(shí)鐘/日歷)
中文描述： 實(shí)時(shí)時(shí)鐘/日歷（EEPROM的實(shí)時(shí)時(shí)鐘/日歷帶有EEPROM）
文件頁(yè)數(shù)： 16/27頁(yè)
文件大?。?/td> 412K
代理商： ISL12025
16
FN6371.2
October 19, 2007
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh watchdog timer, a
STOP condition should be followed to reset the device back
to Standby Power Mode. See Figure 3.
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
compares the level of the V
DD
line versus a preset threshold
voltage (V
RESET
), then generates a RESET pulse if it is
below V
RESET
. The reset pulse will timeout 250ms after the
V
DD
line rises above V
RESET
. If the V
DD
remains below
V
RESET
, then the RESET output will remain asserted low.
Power-up and power-down waveforms are shown in
Figure 4. The LVR circuit is to be designed so the RESET
signal is valid down to V
DD
= 1.0V.
When the LVR signal is active, unless the part has been
switched into the Battery Backup Mode
,
the completion of an
in-progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
operations. See “I
2
C Communications During Battery
Backup and LVR Operation” on page 23.
Serial Communication
Interface Conventions
The device supports the I
2
C Protocol.
Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 16.
Start Condition
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 17.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby Power Mode after a read sequence. A stop
condition can only be issued after the transmitting device
has released the bus. See Figure 17.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting 8-bits.
During the ninth clock cycle, the receiver will pull the SDA
line LOW to acknowledge that it received the 8-bits of data.
See Figure 18.
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
eight bit word. The device will not acknowledge if the slave
address byte is incorrect.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
Standby Power Mode and place the device into a known
state.
TABLE 6.
WD1
WD0
DURATION
1
1
disabled
1
0
250ms
0
1
750ms
0
0
1.75s
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
ISL12025
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ISL12026 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Real Time Clock/Calendar with I2C Bus? and EEPROM
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