參數(shù)資料
型號(hào)： IMSC011-W20S
廠商： 意法半導(dǎo)體
英文描述： Link adaptor
中文描述： 鏈路適配器
文件頁(yè)數(shù)： 14/30頁(yè)
文件大小： 239K
代理商： IMSC011-W20S
IMS C011
/ 30
14
6
Mode 2 parallel interface
The IMS C011provides an interface between a link and a microprocessor style bus.Operation of thelink
adaptor is controlled throughthe parallelinterface buslines
D0-7
by readingand writing variousregisters
in the link adaptor. Registers are selected by
RS0-1
and
RnotW
, and the chip enabled with
notCS
.
For convenience of description, the device connected to the parallel side of thelink adaptor is presumed
to be a microprocessor, although this will not always be the case.
6.1
D0–7
Data is communicated between a microprocessor bus and the link adaptor via thebidirectional bus lines
D0-7
. The busis high impedanceunless thelink adaptor chipis selected and the
RnotW
line is high. The
bus is used by the microprocessor to access status and data registers.
6.2
notCS
The link adaptor chip is selected when
notCS
is low.Register selectors
RS0-1
and
RnotW
must be valid
before
notCS
goes low;
D0-7
must also bevalid ifwriting tothe chip (
RnotW
low). Datais read by thelink
adaptor on the rising edge of
notCS
.
6.3
RnotW
RnotW
, inconjunctionwith
notCS
, selectsthe linkadaptor registersfor readorwritemode. When
RnotW
is high, the contents of an addressed register appear on the data bus
D0-7
; when
RnotW
is lowthe data
on
D0-7
is writtenintotheaddressedregister.The state of
RnotW
islatchedintothelinkadaptorby
notCS
going low; it may be changed before
notCS
returns high, within the timing restrictions given.
6.4
RS0–1
One of four registers is selected by
RS0-1
. A register is addressed by setting up
RS0-1
and then taking
notCS
low; thestateof
RnotW
when
notCS
goeslow determines whethertheregisterwillbe reador writ-
ten. The state of
RS0-1
is latched into the link adaptor by
notCS
going low; it may be changed before
notCS
returns high, within thetiming restrictions given. The register set comprisesa read-only data input
register, a write-only data output register and a read/write status register for each.
RS1
0
0
0
0
1
1
1
1
RS0
0
0
1
1
0
0
1
1
RnotW
1
0
1
0
1
0
1
0
Register
Read data
Invalid
Invalid
Write data
Read input status
Write input status
Read output status
Write output status
Table 6.1
IMS C011 Mode 2 register selection
6.4.1
Input Data Register
This register holds thelast data packetreceived from theserial link. It never contains acknowledge pack-
ets. It contains valid data only whilst the data present flag is set in the input status register. It cannot be
assumed to contain valid data after it has been read; a double read may or may not return valid data on
the secondread. If datapresentisvalid ona subsequentread itindicatesnew data isinthe buffer.Writing
to this register will have no effect.
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