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參數(shù)資料
| 型號： | IMSC011-W20S |
| 廠商： | 意法半導體 |
| 英文描述： | Link adaptor |
| 中文描述： | 鏈路適配器 |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 239K |
| 代理商： | IMSC011-W20S |
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3 System services
/ 30
5
3
System services
System services include all the necessary logic to start up and maintain the IMS C011.
3.1
Power
Power is supplied to the device via the
VDD
and
GND
pins. The supply must be decoupled close to the
chip by at least one 100 nF low inductance (e.g. ceramic) capacitor between
VDD
and
GND
. Four layer
boards are recommended; if two layer boards are used, extra care should be taken in decoupling.
AC noise between
VDD
and
GND
must be kept below 200 mV peak to peak at all frequencies above
100 KHz. AC noise between
VDD
and the ground reference of load capacitances must be kept below
200 mV peakto peak at all frequencies above30 MHz. Input voltages must not exceed specificationwith
respect to
VDD
and
GND
, even during power-up and power-downramping, otherwiselatchupcan occur.
CMOS devices can be permanently damaged by excessive periods of latchup.
3.2
CapMinus
The internally derived power supply for internal clocks requires an external low leakage, low inductance
1 F capacitor to be connected between
VDD
and
CapMinus
. A ceramic capacitor is preferred, with an
impedance less than 3 Ohms between100 KHzand 10 MHz. If a polarisedcapacitor isused the negative
terminal shouldbe connectedto
CapMinus
.TotalPCB track lengthshould be less than 50mm. Theposi-
tiveconnection ofthecapacitormustbeconnecteddirectlyto
VDD
.Connectionsmustnototherwisetouch
power supplies or other noise sources.
Phase–locked
loops
VDD
GND
CapMinus
P.C.B track
P.C.B track
Decoupling
capacitor 1 F
pin
VDD
Figure 3.1
Recommended PLL decoupling
3.3
ClockIn
Transputerfamily components usea standardclock frequency,supplied bythe useronthe
ClockIn
input.
The nominal frequency of this clock for all transputer family components is 5 MHz, regardless of device
type, transputer word length or processor cycle time. High frequency internal clocks are derived from
ClockIn
, simplifying system design and avoiding problems of distributing high speed clocks externally.
Anumberoftransputerfamilydevicesmaybeconnectedtoacommonclock,ormayhaveindividualclocks
providing each one meets the specified stability criteria. In a multi-clock system the relative phasing of
ClockIn
clocks isnot important,dueto theasynchronous natureof the links.Mark/space ratio isunimpor-
tant provided the specified limits of
ClockIn
pulse widths are met.
Oscillator stability is important.
ClockIn
must be derived from a crystal oscillator; RC oscillators are not
sufficiently stable.
ClockIn
must not be distributed through a long chain of buffers.Clock edges must be
monotonic and remain within the specified voltage and time limits.
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| IMSC011-P20S | Link adaptor |
| IMT17-AG6-R | GENERAL PURPOSE DUAL TRANSISTOR |
| IMT17L-AG6-R | GENERAL PURPOSE DUAL TRANSISTOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IMSC012A-P20S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| IMSC11015BK | 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION, S-VID,CMPO RCA,110,1.5U,BK |
| IMSC11015EI | 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION, S-VID,CMPO RCA,110,1.5U,EI |
| IMSCCR815AL | 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION MOD, W/S-VID,CMPO,8P F,1.5U,AL |
| IMSCCR815BK | 制造商:Hubbell Premise Wiring 功能描述: 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION MOD, W/S-VID,CMPO,8P F,1.5U,BK |
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