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參數(shù)資料
| 型號： | IMSC011-W20S |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Link adaptor |
| 中文描述： | 鏈路適配器 |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 239K |
| 代理商： | IMSC011-W20S |
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5 Mode 1 parallel interface
/ 30
13
5.2
Output port
The eight bit parallel output port
Q0-7
can be controlled by a transputer family device via the serial link.
QValid
and
QAck
provide a simple two-wire handshake for this port.
A data packet received on the input link is presented on
Q0-7
; the link adaptor then takes
QValid
high to
initiatethehandshake.Afterreadingdatafrom
Q0-7
,theperipheraldevicesets
QAck
high. The IMS C011
will then send an acknowledge packet out of the serial link to indicate a completed transaction and set
QValid
low to complete the handshake.
Symbol
TLdVQvH
TQdVQvH
TQvHQaH
TQaHQvL
TQaHLaV
TQvLQaL
TQvLQdX
Parameter
Start of link data to
QValid
Data setup
QAck
setup time from
QValid
high
QAck
high to
QValid
low
QAck
high to Ack on link
QAck
hold after
QValid
low
Data hold
Min
11.5
12
0
1.8
0.8
0
11
Nom
Max
Units
bits
ns
ns
bits
bits
ns
bits
Notes
1
2
1
2.5
1,3
1,4
Notes
1 Unit of measurementis one link data bittime; at 10 Mbits/sdata link speed, onebit timeis nomi-
nally 100 ns.
2 Where an existing data output bit is re-written with the same level there will be no glitch in the
output level.
3 Maximum time assumes thereis no datapacket already onthe link. Maximum time with data on
the link is extended by 11 bits.
4 Data output remains valid until overwritten by new data.
Table 5.2
Mode 1 parallel data output
Ack
Data
Data
TLdVQvH
TQvHQaH
LinkIn
QValid
Q0–7
LinkOut
TQdVQvH
TQvLQdX
TQaHQvL
TQvLQaL
QAck
TQaHLaV
Figure 5.2
IMS C011 Mode 1 parallel data output from link adaptor
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IMSC012A-P20S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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| IMSCCR815AL | 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION MOD, W/S-VID,CMPO,8P F,1.5U,AL |
| IMSCCR815BK | 制造商:Hubbell Premise Wiring 功能描述: 制造商:Hubbell Wiring Device-Kellems 功能描述:ISTATION MOD, W/S-VID,CMPO,8P F,1.5U,BK |
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