參數(shù)資料
型號(hào)： IMSC011-W20S
廠商： 意法半導(dǎo)體
英文描述： Link adaptor
中文描述： 鏈路適配器
文件頁(yè)數(shù)： 17/30頁(yè)
文件大小： 239K
代理商： IMSC011-W20S
6 Mode 2 parallel interface
/ 30
17
6.4.2
Input Status Register
Thisregistercontains thedata presentflagand theinterruptenablecontrol bitfor
InputInt
. Thedatapres-
ent flag is set to indicate that data in thedata input buffer is valid. It is reset lowonly when the data input
buffer is read, or by
Reset
. When writing to this register, the data present bit must be written as zero.
Theinterruptenablebit canbesetand resetby writingto thestatus registerwith thisbithighor lowrespec-
tively.Whentheinterrupt enableand datapresentflagsarebothhigh, the
InputInt
outputwillbehigh(sec-
tion 6.5). Resetting interrupt enablewill take
InputInt
low; setting it again before reading the data input
register will set
InputInt
high again. The interrupt enable bit can be read to determine its status.
When writing to this register, bits 2-7 must be written as zero; this ensuresthat they willbe zerowhen the
register is read. Failure to write zeroes to these bits may result inundefined data being returned bythese
bits during a status register read.
&
Interrupt
Enable
Data
Present
InputInt
7
6
5
4
3
2
1
0
Figure 6.3
IMS C011 Mode 2 input status register
6.4.3
Output Data Register
Data written to this link adaptor register is transmitted out of the serial link as a data packet. Data should
onlybe writtentothis registerwhentheoutput readybitin theoutput statusregisterishigh, otherwisedata
already beingtransmitted maybe corrupted.Readingthis registerwillresult inundefined databeingread.
6.4.4
Output Status Register
This register contains the output readyflag and the interrupt enablecontrol bit for
OutputInt
. The output
readyflagis setto indicate thatthedata outputbufferis emptyand alink acknowledgehasbeenreceived.
It is reset low only when data is written to the data output buffer;it is set high by
Reset
. When writing to
this register,the output ready bit must be written as zero.
Theinterruptenablebit canbesetand resetby writingto thestatus registerwith thisbithighor lowrespec-
tively.When the interrupt enableand output readyflags are both high, the
OutputInt
output will be high
(section 6.6).Resettinginterrupt enablewill take
OutputInt
low; settingit againwhilstthe dataoutputreg-
ister is empty will set
OutputInt
high again. The interrupt enablebit can be read to determine its status.
When writing to this register, bits 2-7 must be written as zero; this ensuresthat they willbe zerowhen the
register is read. Failure to write zeroes to these bits may result inundefined data being returned bythese
bits during a status register read.
6.5
InputInt
The
InputInt
output is set high to indicate that a data packet has been received from the serial link. It is
inhibited from going high when the interrupt enablebit in the input status register is low (section 6.4.2).
InputInt
is reset low when data is readfrom theinput data register(section 6.4.1)and by
Reset
(page 7).
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