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參數(shù)資料
| 型號： | IMSC011-W20S |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Link adaptor |
| 中文描述： | 鏈路適配器 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 239K |
| 代理商： | IMSC011-W20S |
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3 System services
/ 30
7
the device. If
ClockIn
is gated to achieve this, its skew must be limited to the value
TDCHSIQH
shown
in table 3.3. The mode of operation (Mode 1, Mode 2) must not be changed dynamically.
SeparateIQ
VDD
ClockIn
GND
Mode
1
1
2
Link Speed Mbits/sec
10
20
10 or 20
Table 3.2
SeparateIQ
mode selection
Symbol
TDCHSIQH
Parameter
Skew from
ClockIn
to
ClockIn
Min
Nom
Max
20
Units
ns
Notes
1
Notes
1 Skew between
ClockIn
arriving on the
ClockIn
pin and on the
SeparateIQ
pin.
Table 3.3
SeparateIQ
3.5
Reset
The
Reset
pin can go high with
VDD
, butmust at no time exceedthe maximumspecified voltagefor
VIH
.
After
VDD
is valid
ClockIn
should be runningfor a minimum period
TDCVRL
before theend of
Reset
. All
inputs, with the exception of
ClockIn
and
SeparateIQ
(plus
LinkSpeed
in mode 2), must be heldin their
inactive state during reset.
Reset
initialises the IMS C011 to the following state:
LinkOut
is held low; the control outputs (
IAck
and
QValid
in Mode 1,
InputInt
and
OutputInt
in Mode 2) are held low; interrupts (Mode 2) are disabled; the
states of
Q0-7
in Mode 1 are unspecified;
D0-7
in Mode 2 are high impedance.
Symbol
TPVRH
TRHRL
TDCVRL
TRLIvH
TRLCSL
Parameter
Power valid before
Reset
Reset
pulse width high
ClockIn
running before
Reset
end
Reset
low before
IValid
high (mode 1)
Reset
low before chip select low (mode 2)
Min
10
8
10
0
0
Nom
Max
Units
ms
ClockIn
ms
ns
ns
Notes
1
2
Notes
1 Full periods of
ClockIn TDCLDCL
required.
2 At power-on reset.
Table3.4
Reset
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