- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1924 > IDT82P2828BHG (IDT, Integrated Device Technology Inc)IC LIU T1/J1/E1 28+1CH 640-PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT82P2828BHG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 72/154頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1/E1 28+1CH 640-PBGA |
| 標(biāo)準(zhǔn)包裝： | 5 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 640-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 640-PBGA-EP（31x31） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2828BHG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當(dāng)前第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Pin Description
24
February 6, 2009
OE
Input
AJ10
OE: Output Enable
OE enables or disables all Line Drivers globally.
A high level on this pin enables all Line Drivers while a low level on this pin places all Line
Drivers in High-Z state and independent from related register settings.
Note that the functionality of the internal circuit is not affected by OE.
If this pin is not used, it should be tied to VDDIO.
This pin can be used to control the transmit impedance state for Hitless protection applica-
tions. Refer to Section 4.4 Hitless Protection Switching (HPS) Summary for details.
TEHWE
Input
(Pull-Up)
AF11
TEHWE: Hardware T1/J1 or E1 Mode Selection Enable
When this pin is open, the T1/J1 or E1 operation mode is selected by TEHW globally.
When this pin is low, the T1/J1 or E1 operation mode is selected by the T1E1 bit (b0,
CHCF,...) on a per-channel basis.
TEHW
Input
(Pull-Up)
AF12
TEHW: Hardware T1/J1 or E1 Mode Selection
When TEHWE is open, this pin selects the T1/J1 or E1 operation mode globally:
Low - E1 mode;
Open - T1/J1 mode.
When TEHWE is low, the input on this pin is ignored.
GPIO[0]
GPIO[1]
Output / Input
AF9
AF10
GPIO: General Purpose I/O [1:0]
These two pins can be defined as input pins or output pins by the DIR[1:0] bits (b1~0, GPIO)
respectively.
When the pins are input, their polarities are indicated by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
When the pins are output, their polarities are controlled by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
RST
Input
AG10
RST: Reset (Active Low)
A low pulse on this pin resets the device. This hardware reset process completes in 2 s max-
imum. Refer to Section 4.1 Reset for an overview on reset options.
MCU Interface
INT
Output
AK16
INT: Interrupt Request
This pin indicates interrupt requests for all unmasked interrupt sources.
The output characteristics (open drain or push-pull internally) and the active level are deter-
mined by the INT_PIN[1:0] bits (b3~2, GCF).
CS
Input
AJ17
CS: Chip Select (Active Low)
This pin must be asserted low to enable the microprocessor interface.
A transition from high to low must occur on this pin for each Read/Write operation and CS
should remain low until the operation is over.
P/S
Input
AG16
P/S: Parallel or Serial Microprocessor Interface Select
P/S selects Serial or Parallel microprocessor interface for the device:
GNDD - Serial microprocessor interface.
VDDIO - Parallel microprocessor interface.
Serial microprocessor interface consists of the CS, SCLK, SDI, SDO pins.
Parallel microprocessor interface consists of the CS, INT/MOT, IM, DS/RD, ALE/AS, R/W/WR,
ACK/RDY, D[7:0], A[10:0] pins.
INT/MOT
Input
(Pull-Up)
AF14
INT/MOT: Intel or Motorola Microprocessor Interface Select
In Parallel microprocessor interface, INT/MOT selects Intel or Motorola microprocessor inter-
face for the device:
GNDD - Parallel Motorola microprocessor interface.
Open - Parallel Intel microprocessor interface.
In Serial microprocessor interface, this pin should be left open.
Name
I / O
Pin No.
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT82P2916BFG | IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088BBG | IC LIU T1/E1/J1 OCTAL 256PBGA |
| IDT82V2041EPPG | IC LIU T1/J1/E1 1CH 44-TQFP |
| IDT82V2042EPFG | IC LIU T1/J1/E1 2CH SHORT 80TQFP |
| IDT82V2044EPFG | IC LIU T1/E1 QUAD SHORT 128-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2916 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel High-Density T1/E1/J1 Line Interface Unit |
| IDT82P2916BFG | 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| IDT82P2916BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
| IDT82P5088BBBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。