Figure-30 Automatic Error Counter Up" />
參數(shù)資料
型號： IDT82P2828BHG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 102/154頁
文件大小： 0K
描述： IC LIU T1/J1/E1 28+1CH 640-PBGA
標準包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應商設備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2828BHG
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
51
February 6, 2009
Figure-30 Automatic Error Counter Updating
3.5.6.2 Manual Error Counter Updating
When the CNT_MD bit (b1, ERR,...) is ‘0’, the Error Counter is
updated manually.
When there is a transition from ‘0’ to ‘1’ on the CNT_STOP bit (b0,
ERR,...), the Error Counter transfers the accumulated error numbers to
the ERRCH and ERRCL registers and the Error Counter will be cleared
to start a new round counting. The ERRCH and ERRCL registers should
be read in the next round of error counting, otherwise they will be over-
written.
When the ERRCH and ERRCL registers are all ‘1’s and there is still
error to be accumulated, the registers will be overflowed. The overflow is
indicated by the CNTOV_IS bit (b0, INTS2,...) and will induce an inter-
rupt reported by INT if not masked by the CNTOV_IM (b0, INTM2,...).
The process of manual Error Counter updating is illustrated in
Figure-31 Manual Error Counter Updating
Read the ERRCH & ERRCL
registers in the next second
TMOV_IS is cleared after a '1' is
written to it
Data in the Error Counter transfers
to the ERRCH & ERRCL registers
The Error Counter is cleared
One second expired?
(TMOV_IS = 1 ?)
Counting
Automatic Error Counter Updating
(CNT_MD = 1)
No
Yes
repeat the
same process
in the next
second
Read the ERRCH & ERRCL
registers in the next round
Data in the Error Counter transfers
to the ERRCH & ERRCL registers
The Error Counter is cleared
A transition from '0' to
'1' on CNT_STOP ?
Counting
Manual Error Counter Updating
(CNT_MD = 0)
No
Yes
repeat the
same
process in
the next
round
(CNT_STOP
must be
cleared
before the
next round)
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