參數(shù)資料
型號： IDT82P2828BHG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 152/154頁
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 28+1CH 640-PBGA
標(biāo)準(zhǔn)包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2828BHG
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Programming Information
97
February 6, 2009
RCF1 - Receive Configuration Register 1
Address: 00BH, 04BH, 08BH, 0CBH, 10BH, 14BH, 18BH, 1CBH, (CH1~CH8)
20BH, 24BH, 28BH, 2CBH, 30BH, 34BH, 38BH, 3CBH, (CH9~CH16)
40BH, 44BH, 48BH, 4CBH, 50BH, 54BH, 58BH, 5CBH, (CH17~CH24)
60BH, 64BH, 68BH, 6CBH, (CH25~CH28)
7CBH (CH0)
Type: Read / Write
Default Value: 01H
Bit
Name
Description
7 - 5
RMF_DEF[2:0] These bits are valid only in Receive Single Rail NRZ Format mode and Receive Dual Rail Sliced mode. They determine the out-
put on the RMFn pin.
000: PRBS/ARB indication when the PRBS/ARB detection is switched to the receive path. Or reserved when the PRBS/ARB
detection is switched to the transmit path. (default)
001: LAIS indication.
010: XOR data of positive and negative sliced data.
011: Recovered clock (RCLK).
100: LEXZ indication.
101: LBPV indication.
110: LEXZ + LBPV indication.
111: LLOS indication.
4
RCK_ES
This bit selects the active edge of the RCLKn pin.
0: Rising edge. (default)
1: Falling edge.
3
RD_INV
This bit determines the active level on the RDn, RDPn and RDNn pins.
0: Active high. (default)
1: Active low.
2
R_CODE
This bit selects the line code rule for the receive path.
0: B8ZS (in T1/J1 mode) / HDB3 (in E1 mode). (default)
1: AMI.
1 - 0
R_MD[1:0]
These bits determines the receive system interface.
00: Receive Single Rail NRZ Format system interface. The data is output on RDn in NRZ format and a 1.544 MHz (in T1/J1
mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn.
01: Receive Dual Rail NRZ Format system interface. The data is output on RDPn and RDNn in NRZ format and a 1.544 MHz (in
T1/J1 mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn. (default)
10: Receive Dual Rail RZ Format system interface. The data is output on RDPn and RDNn in RZ format and a 1.544 MHz (in T1/
J1 mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn.
11: Receive Dual Rail Sliced system interface. The data is output on RDPn and RDNn in RZ format directly after passing through
the Slicer.
765
432
1
0
RMF_DEF2
RMF_DEF1
RMF_DEF0
RCK_ES
RD_INV
R_CODE
R_MD1
R_MD0
相關(guān)PDF資料
PDF描述
IDT82P2916BFG IC LIU T1/E1/J1 16CH SH 484BGA
IDT82P5088BBG IC LIU T1/E1/J1 OCTAL 256PBGA
IDT82V2041EPPG IC LIU T1/J1/E1 1CH 44-TQFP
IDT82V2042EPFG IC LIU T1/J1/E1 2CH SHORT 80TQFP
IDT82V2044EPFG IC LIU T1/E1 QUAD SHORT 128-TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82P2916 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel High-Density T1/E1/J1 Line Interface Unit
IDT82P2916BFG 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:*
IDT82P2916BFG8 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA
IDT82P5088 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter
IDT82P5088BBBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*