參數(shù)資料
型號： IDT82P2828BHG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 124/154頁
文件大小： 0K
描述： IC LIU T1/J1/E1 28+1CH 640-PBGA
標準包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應商設備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2828BHG
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Miscellaneous
71
February 6, 2009
4.1.1
POWER-ON RESET
Power-on reset is initiated during power-up. When all VDD inputs
(1.8V and 3.3V) reach approximately 60% of the standard value of VDD,
power-on reset begins. If MCLK is applied, power-on reset will complete
within 1 ms maximum; if MCLK is not applied, the device remains in
reset state.
4.1.2
HARDWARE RESET
Pulling the RST pin to low will initiate hardware reset. The reset cycle
should be more than 1 s. If the RST pin is held low continuously, the
device remains in reset state.
4.1.3
GLOBAL SOFTWARE RESET
Writing the RST register will initiate global software reset. Once initi-
ated, global software reset completes in 1 s maximum.
4.1.4
PER-CHANNEL SOFTWARE RESET
Writing a ‘1’ to the CHRST bit (b1, CHCF,...) will initiate per-channel
software reset. Once initiated, per-channel software reset completes in 1
s maximum and the CHRST bit (b1, CHCF,...) is self cleared.
This reset is different from other resets, for:
It does not reset the T1E1 bit (b0, CHCF,...). That is, the operation
mode of each channel is not changed;
It does not reset the global registers, state machines and common
pins (including the pins of clock generator, microprocessor inter-
face and JTAG interface);
It does not reset the other channels.
4.2
MICROPROCESSOR INTERFACE
The microprocessor interface provides access to read and write the
registers in the device. The interface consists of:
Serial microprocessor interface;
Parallel Motorola Non-Multiplexed microprocessor interface;
Parallel Motorola Multiplexed microprocessor interface;
Parallel Intel Non-Multiplexed microprocessor interface;
Parallel Intel Multiplexed microprocessor interface.
The microprocessor interface is selected by the P/S, INT/MOT and
IM pins, as shown in Table-27. The interfaced pins in different interfaces
face Timing for the timing characteristics.
Table-27 Microprocessor Interface
P/S
INT/MOT
IM
Microprocessor Interface
Interfaced Pins
GNDD
Open
GNDD
Serial microprocessor interface
CS
, SCLK, SDI, SDO
VDDIO
GNDD
Parallel Motorola Non-Multiplexed microprocessor interface
CS
, DS, R/W, ACK, D[7:0], A[10:0]
Open
Parallel Motorola Multiplexed microprocessor interface
CS
, AS, DS, R/W, ACK, D[7:0], A[10:8]
Open
GNDD
Parallel Intel Non-Multiplexed microprocessor interface
CS
, RD, WR, RDY, D[7:0], A[10:0]
Open
Parallel Intel Multiplexed microprocessor interface
CS
, ALE, RD, WR, RDY, D[7:0], A[10:8]
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