- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2076 > IDT72T36135ML5BBG (IDT, Integrated Device Technology Inc)IC FIFO 1MX18 5NS 240BGA PDF資料下載
參數(shù)資料
| 型號： | IDT72T36135ML5BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 1MX18 5NS 240BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲容量： | 18M（1M x 18） |
| 訪問時間： | 5ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應(yīng)商設(shè)備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36135ML5BBG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
17
FEBRUARY 04, 2009
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of
PAE[1:2] and PAF[1:2] values can be achieved by using a
combination of the
LD, SEN,SCLKandSIinputpins.Programming PAE[1:2]
and
PAF[1:2] proceeds as follows: when LD and SEN are set LOW, data on
theSIinputarewritten,onebitforeachSCLKrisingedge,startingwiththeEmpty
OffsetLSBandendingwiththeFullOffsetMSB.38bitstotalrequired.SeeFigure
19, Serial Loading of Programmable Flag Registers, for the timing diagram for
thismode.
Using the serial method, individual registers cannot be programmed
selectively.
PAE[1:2] and PAF[1:2] can show a valid status only after the
completesetofbits(foralloffsetregisters)hasbeenentered.Theregisterscan
bereprogrammedaslongasthecompletesetofnewoffsetbitsisentered.When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing
LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling
WEN. WhenWEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruptionofserialprogrammingisdesired,itissufficienteithertoset
LDLOW
and deactivate
SENortosetSENLOWanddeactivateLD. OnceLDandSEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising SCLK edge that achieves the above criteria;
PAF[1:2]willbevalidafterthreemorerisingWCLKedgesplustPAF,PAE[1:2]
will be valid after the next three rising RCLK edges plus tPAE.
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn.
PARALLEL MODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programming of
PAE[1:2] and PAF[1:2] values can be achieved by using a
combinationofthe
LD, WCLK,WENandDninputpins. ProgrammingPAE[1:2]
and
PAF[1:2] proceeds as follows: LD and WEN must be set LOW. When
programming the Offset Registers of the TeraSync FIFO’s the number of
programming cycles will be based on the bus width, the following rules apply:
4 enabled write cycles are required to program the offset registers, (2 per
offset). Data on the inputs Dn are written into the Empty Offset Register on the
first two LOW-to-HIGH transition of WCLK. Upon the third and fourth LOW-to-
HIGHtransitionofWCLK,dataarewrittenintotheFullOffsetRegister.SeeFigure
3, Programmable Flag Offset Programming Sequence for more details.
RETRANSMIT FROM MARK OPERATION
The Retransmit from Mark feature allows FIFO data to be read repeatedly
startingatauser-selectedposition.TheFIFOisfirstputintoretransmitmodethat
will‘mark’abeginningwordandalsosetapointerthatwillpreventongoingFIFO
write operations from over-writing retransmit data. The retransmit data can be
read repeatedly any number of times from the ‘marked’ position. The FIFO can
be taken out of retransmit mode at any time to allow normal device operation.
The ‘mark’ position can be selected any number of times, each selection over-
writingthepreviousmarklocation.RetransmitoperationisavailableinbothIDT
standard and FWFT modes.
During IDT standard mode the FIFO is put into retransmit mode by a Low-
to-HightransitiononRCLKwhenthe‘MARK’inputisHIGHand
EF[1:2]isHIGH.
The rising RCLK edge ‘marks’ the data present in the FIFO output register as
thefirstretransmitdata.TheFIFOremainsinretransmitmodeuntilarisingedge
on RCLK occurs while MARK is LOW.
Once a ‘marked’ location has been set (and the device is still in retransmit
mode, MARK is HIGH), a retransmit can be initiated by a rising edge on RCLK
while the retransmit input (
RT) is LOW. REN must be HIGH (reads disabled)
before bringing
RTLOW.Thedeviceindicatesthestartofretransmitsetupby
setting
EF[1:2] LOW, also preventing reads. When EF[1:2] goes HIGH,
retransmitsetupiscompleteandreadoperationsmaybeginstartingwiththefirst
data at the MARK location. Since IDT standard mode is selected, every word
readincludingthefirst‘marked’wordfollowingaretransmitsetuprequiresaLOW
on
REN (read enabled).
Note, write operations may continue as normal during all retransmit
functions, however write operations to the ‘marked’ location will be prevented.
See Figure 17, Retransmit from Mark (IDT standard mode), for the relevant
timingdiagram.
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
edge when the ‘MARK’ input is HIGH and
OR[1:2] is LOW. The rising RCLK
edge ‘marks’ the data present in the FIFO output register as the first retransmit
data. The FIFO remains in retransmit mode until a rising RCLK edge occurs
while MARK is LOW.
Once a marked location has been set (and the device is still in retransmit
mode,MARKisHIGH),aretransmitcanbeinitiatedbyarisingRCLKedgewhile
the retransmit input (
RT)isLOW.RENmustbeHIGH(readsdisabled)before
bringing
RTLOW.Thedeviceindicatesthestartofretransmitsetupbysetting
OR[1:2] HIGH.
When
OR[1:2]goesLOW,retransmitsetupiscompleteandonthenextrising
RCLK edge after retransmit setup is complete, (
RTgoesHIGH),thecontents
of the first retransmit location are loaded onto the output register. Since FWFT
mode is selected, the first word appears on the outputs regardless of
REN, a
LOW on
RENis not required for the first word. Reading all subsequent words
requires a LOW on
REN to enable the rising RCLK edge. See Figure 18,
Retransmit from Mark timing (FWFT mode), for the relevant timing diagram.
Note,theremustbeaminimumof128wordsofdatabetweenthewritepointer
and read pointer when the MARK is asserted. Also, once the MARK is set, the
write pointer will not increment past the “marked” location until the MARK is
deasserted. This prevents “overwriting” of retransmit data.
HSTL/LVTTL I/O
Both the write port and read port are user selectable between HSTL or
LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other
control pins are selectable via SHSTL, see Table 4 for details of groupings.
Note,thatwhenthewriteportisselectedforHSTLmode,theusercanreduce
the power consumption (in stand-by mode by utilizing the
WCS input).
All “Static Pins” must be tied to VCC or GND. These pins are LVTTL only,
and are purely device configuration pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T72115L5BBI | IC FIFO 131072X72 5NS 324-BGA |
| IDT72V06L15J | IC ASYNCH 8192X18 15NS 32PLCC |
| IDT72V2105L15PFI | IC FIFO SUPERSYNCII 15NS 64-TQFP |
| IDT72V2111L15PFI | IC FIFO SS 512X9 15NS 64QFP |
| IDT72V2113L6BC | IC FIFO SUPERSYNCII 6NS 100-BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T36135ML6BB | 功能描述:IC FIFO 1MX18 6NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36135ML6BBI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512KX36 ASYNC 240BGA |
| IDT72T3645L4-4BB | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72T3645L4-4BBG | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72T3645L5BB | 功能描述:IC FIFO 1024X36 5NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。