參數(shù)資料
型號(hào): IDT72T36135ML5BBG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 34/48頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 1MX18 5NS 240BGA
標(biāo)準(zhǔn)包裝: 1
系列: 72T
功能: 異步,同步
存儲(chǔ)容量: 18M(1M x 18)
訪問(wèn)時(shí)間: 5ns
電源電壓: 2.375 V ~ 2.625 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 240-BGA
供應(yīng)商設(shè)備封裝: 240-PBGA(19x19)
包裝: 托盤(pán)
其它名稱: 72T36135ML5BBG
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
4
FEBRUARY 04, 2009
DESCRIPTION (CONTINUED)
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (
OE) and Synchronous Read
Chip Select pin (
RCS)areprovidedontheFIFO.TheSynchronousReadChip
SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture. Special consideration should be taken into
account for JTAG testing since the device is a MCM. Please see JTAG section
for further details.
The TeraSync FIFO has the capability of operating its ports (write and/or
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input HSTL is also provided, this allows the user to
selectHSTLoperationforotherpinsonthedevice(notassociatedwiththewrite
or read ports).
TheIDT72T36135MisfabricatedusingIDT’shighspeedsubmicronCMOS
technology.
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