參數(shù)資料
型號(hào)： IDT72T36135ML5BBG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 41/48頁
文件大?。?/td> 0K
描述： IC FIFO 1MX18 5NS 240BGA
標(biāo)準(zhǔn)包裝： 1
系列： 72T
功能： 異步，同步
存儲(chǔ)容量： 18M（1M x 18）
訪問時(shí)間： 5ns
電源電壓： 2.375 V ~ 2.625 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 240-BGA
供應(yīng)商設(shè)備封裝： 240-PBGA（19x19）
包裝： 托盤
其它名稱： 72T36135ML5BBG
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
46
FEBRUARY 04, 2009
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased by connecting together the control signals of
multiple devices plus using external gating logic. Status flags can be gated and
detected from the gate output. The
EF[1:2], FF[1:2], PAE[1:2], and PAF[1:2]
flagsshouldbegatedusinglogicalgatestoremovethepossibilityofclockskew
between the two device(s) outputs.
Figure 32 demonstrates a width expansion using two IDT72T36135M
devices. D0 - D35 from each device form a 72-bit wide input bus and Q0-Q35
fromeachdeviceforma72-bitwideoutputbus.Anywordwidthcanbeattained
by adding additional IDT72T36135M devices.
NOTES:
1. An OR gate is used for FWFT mode, AND gate for IDT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
4.
PAE/PAF[1:2] optional, see section of external gating of output flags.
5. Recommend IDT74LVC32A 2-Input Positive OR Gate. Recommend IDT74LVC08A 2-Input AND Gate.
Figure 32. Block Diagram of 524,288 x 72 Width Expansion
WRITE CLOCK (WCLK)
m + n
mn
MASTER RESET (MRS)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST FULL (PAF) #1
PROGRAMMABLE ALMOST FULL (PAF) #2
FULL FLAG/INPUT READY (FF/IR)) #2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
m
LOAD (LD)
IDT
72T36135M
FULL FLAG/INPUT READY (FF/IR) #1
PARTIAL RESET (PRS)
6723 drw39
FULL FLAG/INPUT READY (FF/IR) #2
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
READ CHIP SELECT (RCS)
SERIAL CLOCK
(SCLK)
IDT
72T36135M
PROGRAMMABLE ALMOST FULL (PAF) #2
PROGRAMMABLE ALMOST FULL (PAF) #1
AND
GATE
AND
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE ALMOST EMPTY (PAE) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
GATE
(1)
PROGRAMMABLE ALMOST EMPTY (PAE) #2
AND
GATE
PROGRAMMABLE ALMOST EMPTY (PAE) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
GATE
(1)
PROGRAMMABLE ALMOST EMPTY (PAE) #1
AND
GATE
(1)
AND
GATE
AND
GATE
AND
GATE
AND
GATE
(1)
FULL FLAG/INPUT READY
EMPTY FLAG/OUTPUT READY
PROGRAMMABLE ALMOST FULL
PROGRAMMABLE ALMOST
EMPTY
(EF/OR)
(PAE)
(FF/IR)
(PAF)
FIFO#1
FIFO#2
GATE
(1)
GATE
(1)
GATE
(1)
AND
GATE
AND
GATE
(4)
GATE
(1)
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T36135M can easily be adapted to applications requiring depths
greater than and 524,288 with an 36-bit bus width. In FWFT mode, the FIFOs
canbeconnectedinseries(thedataoutputsofoneFIFOconnectedtothedata
inputsofthenext)withnoexternallogicnecessary. Theresultingconfiguration
provides a total depth equivalent to the sum of the depths associated with each
single FIFO. Figure 33 shows a depth expansion using two IDT72T36135M
devices.
For depth expansion mode option #1, “l(fā)ogical OR gates” need to be used
todrivetheactivelowinput
WENandRENpinsrespectivelyfromtheactivelow
output
OR[1:2] and IR[1:2] pins. Two sets of OR gates are used in this mode
to derive a feedback loop to the
RENandWENpinstoavoidwritingorreading
to/from a device when the device is not ready to accept data. The 2nd row of
OR gates take in the
IRorOR pin’sstatusandallowfordatatobewritten/read
to the next FIFO in the chain. If the
IR or OR pins are low, this will enable the
device to accept writes or reads from the next device in line. To use this mode,
the FIFO device’s clock speed depends on the added prop delay of the “OR”
gatesandsetuptimebetweenthetwoFIFOdevices.Example,ifthe“OR”gates
being used have a combined 10ns propagation delay, a 1ns jitter budget, and
1nsclockskewmargin,12nsmustbetakenintoaccountduringeachclockcycle.
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