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參數(shù)資料
| 型號(hào)： | IDT72T36135ML5BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 6/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO 1MX18 5NS 240BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲(chǔ)容量： | 18M（1M x 18） |
| 訪問時(shí)間： | 5ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應(yīng)商設(shè)備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36135ML5BBG |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T36135M 2.5V 18M-BIT TeraSync
36-BIT FIFO
524,288 x 36
14
FEBRUARY 04, 2009
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T36135M support two different timing modes of operation: IDT
Standard mode or First Word Fall Through (FWFT) mode. The selection of
which mode will operate is determined during Master Reset, by the state of the
FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (
EF[1:2])toindicatewhether
ornotthereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction
(
FF[1:2])toindicatewhetherornottheFIFOhasanyfreespaceforwriting.In
IDT Standard mode, every word read from the FIFO, including the first, must
be requested using the Read Enable (
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR[1:2]) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (
IR[1:2])
to indicate whether or not the FIFO has any free space for writing. In the FWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK
rising edges,
REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (
REN) and RCLK.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags,
FF[1:2], PAF[1:2], PAE[1:2], and EF[1:2]
operate in the manner outlined in Table 2. To write data into to the FIFO, Write
Enable(
WEN)mustbeLOW.DatapresentedtotheDATAINlineswillbeclocked
intotheFIFOonsubsequenttransitionsoftheWriteClock(WCLK).Afterthefirst
write is performed, the Empty Flag (
EF[1:2])willgoHIGH.Subsequentwrites
willcontinuetofilluptheFIFO.TheProgrammableAlmost-Emptyflag(
PAE[1:2])
will go HIGH after n + 1 words have been loaded into the FIFO, where n is the
emptyoffsetvalue.Thedefaultsettingforthesevaluesarestatedinthefootnote
of Table 1. This parameter is also user programmable. See section on
Programmable Flag Offset Loading.
ContinuingtowritedataintotheFIFOwillcausetheProgrammableAlmost-
Full flag (
PAF[1:2])togoLOW.Again,ifnoreadsareperformed,thePAF[1:2]
will go LOW. The offset “m” is the full offset value. The default setting for these
values are stated in the footnote of Table 1. This parameter is also user
programmable. See section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (
FF[1:2])willgoLOW,inhibitingfurther
write operations. If no reads are performed after a reset,
FF[1:2] will go LOW
after D writes to the FIFO.
If the FIFO is full, the first read operation will cause
FF[1:2] to go HIGH.
Subsequent read operations will cause
PAF[1:2]togoHIGHattheconditions
described in Table 2. If further read operations occur, without write operations,
PAE[1:2]willgoLOWwhentherearenwordsintheFIFO,wherenistheempty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
When the last word has been read from the FIFO, the
EF[1:2] will go LOW
inhibiting further read operations.
REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the
EF[1:2] and FF[1:2] outputs
are double register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
10, 11, 12 and 17.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags,
IR[1:2], PAF[1:2], PAE[1:2], and OR[1:2]
operate in the manner outlined in Table 3. To write data into to the FIFO,
WEN
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
onsubsequenttransitionsofWCLK.Afterthefirstwriteisperformed,theOutput
Ready (
OR[1:2])flagwillgoLOW.Subsequentwriteswillcontinuetofillupthe
FIFO.
PAE[1:2]willgoHIGHaftern + 2wordshavebeenloadedintotheFIFO,
wherenistheemptyoffsetvalue.Thedefaultsettingforthesevaluesarestated
inthefootnoteofTable1.Thisparameterisalsouserprogrammable.Seesection
on Programmable Flag Offset Loading.
When the FIFO is full, the Input Ready (
IR[1:2])flagwillgoHIGH,inhibiting
further write operations. If no reads are performed after a reset,
IR[1:2]willgo
HIGH after D writes to the FIFO. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.
IftheFIFOisfull,thefirstreadoperationwillcausethe
IR[1:2]flagtogoLOW.
Subsequentreadoperationswillcausethe
PAF[1:2]togoHIGHattheconditions
described in Table 3. If further read operations occur, without write operations,
the
PAE[1:2] will go LOW when there are n + 1 words in the FIFO, where n is
the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO,
OR[1:2]will
go HIGH inhibiting further read operations.
REN is ignored when the FIFO is
empty.
When configured in FWFT mode, the
OR[1:2] flagoutputistripleregister-
buffered, and the
IR[1:2]flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 13, 14,
15 and 18.
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| IDT72T36135ML6BB | 功能描述:IC FIFO 1MX18 6NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T36135ML6BBI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 512KX36 ASYNC 240BGA |
| IDT72T3645L4-4BB | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72T3645L4-4BBG | 功能描述:IC FIFO 1024X36 4-4NS 208-BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72T3645L5BB | 功能描述:IC FIFO 1024X36 5NS 208-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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