
Internet Data Sheet
Rev. 1.01, 2006-09
03292006-ZZHP-PR83
5
HYS72T[32/64]xxxHP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
1.2
Description
The QIMONDA HYS72T[32/64]xxxHP–[3S/3.7]–A module
family are Registered DIMM (RDIMM with parity) with 30.00
mm height based on DDR2 technology. DIMMs are available
as ECC modules in 32M
×
72 (256 Mbyte) and 64M x 72
(512 MByte) organization and density, intended for mounting
into 240-Pin connector sockets.
The memory array is designed with 256-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E
2
PROM device using the 2-pin I
2
C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
TABLE 4
Ordering Information for RoHS Compliant Products
TABLE 5
Address Format
Product Type
1)
1) All Product Types end with a place code, designating the silicon die revision. Example: HYS72T64020HP–3.7–A, indicating Rev. “A” dies
are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see
Chapter 6
of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–12–G0”, where
4200P means Very Low Profile Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address
Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD
Revision 1.2 and produced on the Raw Card “G”
Compliance Code
2)
Description
SDRAM Technology
PC2-5300
HYS72T32000HP–3S–A
HYS72T64001HP–3S–A
HYS72T64020HP–3S–A
PC2-4200
HYS72T32000HP–3.7–A
HYS72T64001HP–3.7–A
HYS72T64020HP–3.7–A
256MB 1R
×
8 PC2–5300P–555–12–F0
512MB 1R
×
4 PC2–5300P–555–12–H0
512MB 2R
×
8 PC2–5300P–555–12–G0
1 Rank, ECC
1 Rank, ECC
2 Rank, ECC
256 Mbit (
×
8)
256 Mbit (
×
4)
256 Mbit (
×
8)
256MB 1R
×
8 PC2–4200P–444–12–F0
512MB 1R
×
4 PC2–4200P–444–12–H0
512MB 2R
×
8 PC2–4200P–444–12–G0
1 Rank, ECC
1 Rank, ECC
2 Rank, ECC
256 Mbit (
×
8)
256 Mbit (
×
4)
256 Mbit (
×
8)
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of
SDRAMs
# of row/bank/columns bits
Raw Card
256 MB
512 MB
512 MB
32M
×
72
64M
×
72
64M
×
72
1
1
2
ECC
ECC
ECC
9
18
18
13/2/10
13/2/11
13/2/10
F
H
G