參數(shù)資料
型號(hào)： HYS72T32000HP
廠商： QIMONDA
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 240針DDR2 SDRAM的注冊(cè)模塊
文件頁(yè)數(shù)： 17/53頁(yè)
文件大?。?/td> 1264K
代理商： HYS72T32000HP
Internet Data Sheet
Rev. 1.01, 2006-09
03292006-ZZHP-PR83
17
HYS72T[32/64]xxxHP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.3
AC Characteristics
This chapter describes the AC characteristics.
3.3.1
Speed Grades Definitions
This chapter contains the Speed Grade Definition tables.
TABLE 14
Speed Grade Definition Speed Bins for DDR2–667D
TABLE 15
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
DDR2–667D
Unit
Notes
IFX Sort Name
–3S
CAS-RCD-RP latencies
5–5–5
t
CK
Parameter
Symbol
Min.
Max.
—
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
5
3.75
3
45
60
15
15
8
8
8
70000
—
—
—
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Speed Grade
DDR2–533C
Unit
Note
IFX Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
t
CK
Parameter
Symbol
Min.
Max.
—
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
t
CK
t
CK
t
CK
t
RAS
t
RC
5
3.75
3.75
45
60
8
8
8
70000
—
ns
ns
ns
ns
ns
1)2)3)4)
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
1)2)3)4)5)
1)2)3)4)
相關(guān)PDF資料
PDF描述
HYS72T32000HR 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-2.5-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3.7-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3S-A 240-Pin Registered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T32000HR 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-2.5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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