- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385436 > HYS72T32000HP (QIMONDA) 240-Pin Registered DDR2 SDRAM Modules PDF資料下載
參數(shù)資料
| 型號： | HYS72T32000HP |
| 廠商： | QIMONDA |
| 英文描述： | 240-Pin Registered DDR2 SDRAM Modules |
| 中文描述： | 240針DDR2 SDRAM的注冊模塊 |
| 文件頁數(shù)： | 25/53頁 |
| 文件大?。?/td> | 1264K |
| 代理商： | HYS72T32000HP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
Internet Data Sheet
Rev. 1.01, 2006-09
03292006-ZZHP-PR83
25
HYS72T[32/64]xxxHP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Data hold skew factor
Average periodic refresh Interval
t
QHS
t
REFI
—
—
—
75
400
7.8
3.9
—
ps
μ
s
μ
s
ns
14)15)
16)21)
Auto-Refresh to Active/Auto-Refresh
command period
Auto-Refresh to Active/Auto-Refresh
command period
Auto-Refresh to Active/Auto-Refresh
command period
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
t
RFC
17)
t
RFC
105
—
ns
18)
t
RFC
127.5
—
ns
19)
t
RFC
197.5
—
ns
20)
t
RP
t
RP
t
RPRE
t
RPST
t
RRD
t
RP
+ 1
t
CK
15 + 1tCK
0.9
0.40
7.5
10
7.5
0.25 x
t
CK
0.40
15
—
—
1.1
0.60
—
—
—
—
0.60
—
ns
ns
t
CK
t
CK
ns
ns
ns
t
CK
t
CK
ns
14)
14)
14)21)
16)23)
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
Write recovery time for write with Auto-
Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
1) For details and notes see the relevant QIMONDA component data sheet
2)
V
DDQ
= 1.8 V
±
0.1 V;
V
DD
= 1.8 V
±
0.1 V. See notes
5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
7) The output timing reference voltage level is
V
TT
.
t
RTP
t
WPRE
t
WPST
t
WR
22)
WR
t
WR
/
t
CK
t
CK
23)
t
WTR
t
XARD
7.5
2
—
—
ns
t
CK
24)
25)
t
XARDS
6 – AL
—
t
CK
25)
t
XP
2
—
t
CK
t
XSNR
t
XSRD
t
RFC
+10
200
—
—
ns
t
CK
Parameter
Symbol
DDR2–533
Unit
Note
1)2)3)4)5)
6)7)
Min.
Max.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T32000HR | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-2.5-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3.7-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3S-A | 240-Pin Registered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T32000HR | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-2.5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。