參數(shù)資料
型號(hào)： HYS72T32000HP
廠商： QIMONDA
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 240針DDR2 SDRAM的注冊(cè)模塊
文件頁(yè)數(shù)： 26/53頁(yè)
文件大?。?/td> 1264K
代理商： HYS72T32000HP
Internet Data Sheet
Rev. 1.01, 2006-09
03292006-ZZHP-PR83
26
HYS72T[32/64]xxxHP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
8) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (
t
,
t
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for
t
CL
and
t
CH
).
13) The
t
HZ
,
t
RPST
and
t
LZ
,
t
RPRE
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(
t
t
t
t
).
t
and
t
transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range between 85
°
C
and 95
°
C.
15) 0 °C
≤
T
CASE
≤
85
°
C
16) 85
°
C
<
T
CASE
≤
95
°
C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
19) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
20) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
21) The
t
RRD
timing parameter depends on the page size of the DRAM organization. See.
22) The maximum limit for the
t
parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
23) WR must be programmed to fulfill the minimum requirement for the
t
timing parameter, where
WR
[cycles] =
t
(ns)/
t
(ns) rounded
up to the next integer value.
t
= WR + (
t
/
t
). For each of the terms, if not already an integer, round to the next highest integer.
t
CK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
24) Minimum
t
WTR
is two clocks when operating the DDR2-SDRAM at frequencies
≤ 200 ΜΗ
z.
25) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing
t
XARD
can be used. In “l(fā)ow active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing
t
XARDS
has to be satisfied.
相關(guān)PDF資料
PDF描述
HYS72T32000HR 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-2.5-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3.7-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3S-A 240-Pin Registered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T32000HR 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-2.5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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