參數(shù)資料
型號(hào)： HYE25L128160AC-7.5
廠商： INFINEON TECHNOLOGIES AG
英文描述： HEX DIE SET,.052/.068/.178/.25
中文描述： BJAWBMSpecialty DRAM的移動(dòng)RAM
文件頁(yè)數(shù)： 19/50頁(yè)
文件大?。?/td> 980K
代理商： HYE25L128160AC-7.5
HYB/E 25L128160AC
128-MBit Mobile-RAM
INFINEON Technologies
19
2003-02
1RWHV
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests are referenced to the 0.9 V crossover point for VDDQ = 1.8 V components. The
transition time is measured between
9
IH
and
9
IL
. All AC measurements assume
W
T
= 1 ns with the
AC output load circuit (details will be defined later). Specified
W
and
W
parameters are
measured with a 30 pF only, without any resistive termination and with a input signal of 1V / ns
edge rate.
3. If clock rising time is longer than 1 ns, a time (
W
T
/2 - 0.5) ns has to be added to this parameter.
4. If
W
is longer than 1 ns, a time (
W
- 1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows:
WKHQXPEHURIFORFNF\FOH VSHFLILHGYDOXHRIWLPLQJSHULRGFRXQWHGLQIUDFWLRQVDVDZKROH
QXPEHU
6. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.
7. The write recovery time of twr = 14 ns cycles allows the use of one clock cycle for the write
recovery time when the memory operation frequency is equal or less than 72MHz. For all
memory operation frequencies higher than 72MHz two clock cycles for twr are mandatory.
INFINEON recommends to use two clock cylces for the write recovery time in all applications.
30 pF
I/O
Measurement conditions for
t
AC
and
t
OH
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYE25L128160AC-8 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES
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