參數(shù)資料
型號(hào): HYB18H512321BF
廠商: QIMONDA
英文描述: 512-Mbit GDDR3 Graphics RAM
中文描述: 512兆GDDR3顯卡內(nèi)存
文件頁(yè)數(shù): 36/43頁(yè)
文件大?。?/td> 1344K
代理商: HYB18H512321BF
HYB18H512321BF
512-Mbit GDDR3
Internet Data Sheet
Rev. 1.1, 2007-09
05292007-WAU2-UU95
36
Delay from AREF to next
ACT/ AREF
Self Refresh Exit time
Power Down Exit time
Other Timing Parameters
RES to CKE setup timing
RES to CKE hold timing
Termination update Keep
Out timing
Rev. ID EMRS to DQ on
timing
Rev. ID EMRS to DQ off
timing
1) DLL on mode ( -8/10/-11/-12/-14
f
CK(Min)
= 400 MHz)
2)
t
HP
is the lesser of
t
CL
minimum and
t
CH
minimum actually applied to the device CLK, CLK inputs
3) This value of tMRD applies only to the case where the “DLL reset” bit is not activated
4)
t
MRD
is defined from MRS to any other command then READ
5)
t
RASmax
is 8
×
t
REF
6)
t
RCDWR(Min)
may not drop below 2
×
t
CK
7)
t
CCD
is either for gapless consecutive reads or gapless consecutive writes. BL =4
8) WTR and
t
WR
start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal
9) Please round up
t
RTW
to the next integer of
t
CK
10) This parameter is defined per byte
t
RFC
52.0
52.0
52.0
52.0
52.0
ns
t
XSC
t
XPN
1000
7
1000 —
7
1000 —
7
1000 —
7
1000
6
t
CK
t
CK
t
ATS
t
ATH
t
KO
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
ns
ns
ns
t
RIDon
20
20
20
20
20
ns
t
RIDoff
20
20
20
20
20
ns
Parameter
CAS latency Symbol
Limit Values
Unit Note
-8
–10
–11
–12
–14
Min
Max
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
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