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參數(shù)資料
| 型號： | HYB18H512321BF |
| 廠商： | QIMONDA |
| 英文描述： | 512-Mbit GDDR3 Graphics RAM |
| 中文描述： | 512兆GDDR3顯卡內(nèi)存 |
| 文件頁數(shù)： | 18/43頁 |
| 文件大?。?/td> | 1344K |
| 代理商： | HYB18H512321BF |
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HYB18H512321BF
512-Mbit GDDR3
Internet Data Sheet
Rev. 1.1, 2007-09
05292007-WAU2-UU95
18
4.2
Extended Mode Register Set Command (EMRS1)
FIGURE 6
Extended Mode Register Set Command
The Extended Mode Register is used to set the output driver
impedance value, the termination impedance value, the Write
Recovery time value for Write with Autoprecharge. It is used
as well to enable/disable the DLL, to issue the Vendor ID and
to enable/disable the Low Power mode. There is no default
value for the Extended Mode Register. Therefore it must be
written after power up to operate the GDDR3 Graphics RAM.
The Extended Mode Register can be programmed by
performing a normal Mode Register Set operation and setting
the BA0 bit to HIGH and BA1,BA2 bits to LOW. All other bits
of the EMR register are reserved and should be set to LOW.
The Extended Mode Register must be loaded when all banks
are idle and no burst are in progress. The controller must wait
the specified time
t
MRD
before initiating any subsequent
operation (
Figure 9
).
The timing of the EMRS command operation is equivalent to
the timing of the MRS command operation.
CLK#
CLK
RAS#
CKE
CAS#
WE#
A0-A11
BA0
1
Don't Care
COD: Code to be loaded into
the register
CS#
COD
BA1, BA2
0
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