HYB18H512321BF
512-Mbit GDDR3
Internet Data Sheet
Rev. 1.1, 2007-09
05292007-WAU2-UU95
3
1
Overview
This chapter lists all main features of the product family HYB18H512321BF and the ordering information.
1.1
Features
2.0 V
V
DDQ
IO voltage HYB18H512321BF–08/10
2.0 V
V
DD
core voltage HYB18H512321BF–08/10
1.8 V
V
DDQ
IO voltage HYB18H512321BF–11/12/14
1.8 V
V
DD
core voltage HYB18H512321BF–11/12/14
Organization: 2048K
×
32
×
8 banks
4096 rows and 512 columns (128 burst start locations) per
bank
Differential clock inputs (CLK and CLK)
CAS latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17
Write latencies of 3, 4, 5, 6, 7
Burst sequence with length of 4, 8.
4n pre fetch
Short RAS to CAS timing for Writes
t
RAS
Lockout support
t
WR
programmable for Writes with Auto-Precharge
Data mask for write commands
Single ended READ strobe (RDQS) per byte. RDQS edge-
aligned with READ data
Single ended WRITE strobe (WDQS) per byte. WDQS
center-aligned with WRITE data
DLL aligns RDQS and DQ transitions with Clock
Programmable IO interface including on chip termination
(ODT)
Autoprecharge option with concurrent auto precharge
support
8k Refresh (32ms)
Autorefresh and Self Refresh
PG–TFBGA–136 package (10mm
×
14mm)
Calibrated output drive. Active termination support
RoHS Compliant Product
1)
TABLE 1
Ordering Information
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Part Number
1)
1) HYB: designator for memory components
18H:
V
DDQ
= 1.8 V
512: 512-Mbit density
32: Organization
B: Product revision
F: Lead- and Halogen-Free
Organisation
Clock (MHz)
Package
HYB18H512321BF–11/12/14
HYB18H512321BF–08/10
×
32
1200/1000/900/800
/700
PG–TFBGA–136