參數(shù)資料
型號(hào)： HYB18H512321BF
廠商： QIMONDA
英文描述： 512-Mbit GDDR3 Graphics RAM
中文描述： 512兆GDDR3顯卡內(nèi)存
文件頁數(shù)： 24/43頁
文件大?。?/td> 1344K
代理商： HYB18H512321BF
HYB18H512321BF
512-Mbit GDDR3
Internet Data Sheet
Rev. 1.1, 2007-09
05292007-WAU2-UU95
24
5.3
DC & AC Logic Input Levels
TABLE 13
DC & AC Logic Input Levels (0 °C
≤
T
c
≤
85 °C)
Power Supply Voltage
Power Supply Voltage for I/O Buffer
Reference Voltage
Output Low Voltage
Input leakage current
CLK Input leakage current
Output leakage current
1)
V
DDQ
tracks with
V
DD
. AC parameters are measured with
V
DD
and
V
DDQ
tied together.
2) HYB18H512321BF–11/12/14
3) HYB18H512321BF–08/10
4)
V
REF
is expected to equal 70% of
V
for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise
on
V
REF
may not exceed ±2%
V
REF
(DC). Thus, from 70% of
V
DDQ
,
V
REF
is allowed ± 19mV for DC error and an additional ± 27mV for AC
noise.
5)
I
IL
and
I
OL
are measured with ODT disabled.
V
DD
,
V
DDA
V
DDQ
V
REF
V
OL(DC)
I
IL
I
ILC
I
OL
1.7
1.7
0.69*
V
DDQ
—
–5.0
–5.0
–5.0
1.8
1.8
—
—
—
—
—
1.9
1.9
0.71*
V
DDQ
0.8
+5.0
+5.0
+5.0
V
V
V
V
μΑ
μΑ
μΑ
1)3)
1)3)
4)
5)
5)
Parameter
Symbol
Limit Values
Unit
Note
Min.
Max.
Input logic high voltage, DC
Input logic low voltage, DC
Input logic high voltage, AC
Input logic low voltage, AC
Input logic high, DC, RESET pin
Input logic low, DC, RESET pin
Input Logic High, DC, MF pin
Input Logic Low,DC, MF pin
V
IH
(DC)
V
IL
(DC)
V
IH
(AC)
V
IL
(AC)
V
IHR
(DC)
V
ILR
(DC)
V
IHMF
(DC)
V
ILMF
(DC)
V
REF
+ 0.15
—
V
REF
+ 0.25
—
0.65
×
V
DDQ
-0.3
V
DD
–0.3
—
V
REF
-0.15
—
V
REF
- 0.25
V
DDQ
+ 0.3
0.35
×
V
DDQ
V
DD
+ 0.3
0
V
V
V
V
V
V
V
V
1)
1) The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to
maintain a valid level.
2) Input slew rate = 3 V/ns. If the input slew rate is less than 3 V/ns, input timing may be compromised. All slew rates are measured between
V
IL
(DC) and
V
IH
(DC).
3)
V
overshoot:
V
(max) =
V
+0.5V for a pulse width
≤
500ps and the pulse width cannot be greater than 1/3 of the cycle rate.
V
IL
undershoot:
V
IL
(min) = 0 V for a pulse width
≤
500ps and the pulse width cannot be greater than 1/3 of the cycle rate.
4) The MF pin must be hard-wired on board to either
V
DD
or
V
SS
.
1)
2)3)
2)3)
4)
Parameter
Symbol
Limit Values
Unit
Note
Min.
Typ.
Max.
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