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參數(shù)資料
| 型號： | HYB18H512321BF |
| 廠商： | QIMONDA |
| 英文描述： | 512-Mbit GDDR3 Graphics RAM |
| 中文描述： | 512兆GDDR3顯卡內(nèi)存 |
| 文件頁數(shù)： | 13/43頁 |
| 文件大?。?/td> | 1344K |
| 代理商： | HYB18H512321BF |
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HYB18H512321BF
512-Mbit GDDR3
Internet Data Sheet
Rev. 1.1, 2007-09
05292007-WAU2-UU95
13
4
Functional Description
4.1
Mode Register Set Command (MRS)
FIGURE 2
Mode Register Set Command
The Mode Register stores the data for controlling the
operation modes of the memory. It programs CAS latency,
test mode, DLL Reset , the value of the Write Latency and the
Burst length. The Mode Register must be written after power
up to operate the SGRAM. During a ModeRegister Set
command the address inputs are sampled and stored in the
Mode Register. The Mode Register content can only be set or
changed when the chip is in Idle state. For non-READ
commands following a Mode Register Set a delay of
t
MRD
must be met.
The Mode Register Bitmap is supported in two configurations.
The first configuration is intended to support the Mid-Range-
Speed application. The second configuration supports higher
clock cycles for CAS latency and is therefore prepared to
support high-speed application. The selected configuration is
defined by Bit0 of EMRS2.
CLK#
CLK
RAS#
CKE
CAS#
WE#
A0-A11
BA0
0
Don't Care
COD: Code to be loaded into
the register
CS#
COD
BA1, BA2
0
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相關代理商/技術參數(shù) |
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| HYB18H512321BF-08/10 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:512-Mbit GDDR3 Graphics RAM |
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| HYB18L128160BF | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:DRAMs for Mobile Applications 128-Mbit Mobile-RAM |
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