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參數(shù)資料
| 型號： | HV7121B |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | CMOS IMAGE SENSOR With 8-bit ADC |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數(shù)： | 4/30頁 |
| 文件大?。?/td> | 446K |
| 代理商： | HV7121B |
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HV7121B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 4 1999 Hyundai System IC Division
INPUT / OUTPUT AC CHARACTERISTICS
l
All output timing delays are measured with output load 60[pF].
l
Output delay include the internal clock path delay[6ns] and output driving delay that changes in
respect to the output load, the operating environment, and a board design.
l
Due to the variable valid time delay of the output, output signals may be latched in the negative
edge of MCLK for the stable data transfer between the image sensor and a host for less than
15MHz operation.
MCLK to HSYNC/VSYNC Timing
T1 : MCLK rising to HSYNC/VSYNC Valid maximum Time : 18ns [output load: 60pF]
T2 : HSYNC/VSYNC Valid Time : minimum 1Clock(subject to T1, T2 timing rule)
MCLK to DATA Timing
T3 : MCLK rising to DATA Valid maximum Time : 18ns [output load: 60pF]
Note
) HSYNC signal is high when valid data is on the DATA bus.
MCLK
HSYNC/VSYNC
T2
T1
T1
T3
DATA[7:0]
Valid DATA
MCLK
T3
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相關(guān)代理商/技術(shù)參數(shù) |
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| HV7121B-COB | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:CMOS IMAGE SENSOR With 8-bit ADC |
| HV7121B-COF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:CMOS IMAGE SENSOR With 8-bit ADC |
| HV7121GP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sensor |
| HV712PG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| HV712X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
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