參數(shù)資料
型號(hào)： HV7121B
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： CMOS IMAGE SENSOR With 8-bit ADC
中文描述： SPECIALTY ANALOG CIRCUIT, CQCC48
封裝： CERAMIC, LCC-48
文件頁(yè)數(shù)： 18/30頁(yè)
文件大?。?/td> 446K
代理商： HV7121B
HV7121B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 18 1999 Hyundai System IC
Division
(9) VSYNC Blanking Time Register
Higher byte : Address 22h, default : 00h, R/W)
Lower byte : Address 23h, default : 03h, R/W)
The VSYNC blank, and time defines VSYNC active duration in pixel unit .
Note : HSYNC blanking, VSYNC blank are used to fit the CMOS sensor display timing to external timing
requirements.
(10) Integration time Register
High byte : Address 25h, default : 00h, R/W)
Middle byte : Address 26h, default : 01h, R/W)
Low byte : Address 27h, default : f4h, R/W)
Each pixel has a photo diode in which the incoming photons are converted to electrons. Integration time mean
exposure time so these registers defines exposure time.
According to settings
int_sel
of Mode B register, the integration time is controlled with line or pixel unit.
Small value means short exposure time and large value means long exposure time for bright condition.
The value should be large for dark condition. Default value setting 500 lines, this value is useful for normal
office condition. If you stay in outdoor condition, this value should be decreased. But under dark condition, this
value should be increased to get a good image quality. Increasing value may decrease frame rate. Finally,
integration time is very important for frame rate and image quality.
For line mode exposure, register 26h and 27h are used. For pixel mode exposure, all three register 25h ~ 27h
are used. To control exposure time precisely, the pixel mode should be used. This register may be used for
Auto Exposure control.
(11) Operating Clock Divider (Address 28h, default:00h, R/W)
This register generates divided digital clock depending on the settings
clk_div
[3:0], digital block can divide
MCLK down by 1 through 2048 as shown in Table 1.
clk_div
[3:0]
0000
no division
0001
MCLK/2
0010
MCLK/4
0011
MCLK/8
0100
MCLK/16
0101
MCLK/32
units
clk_div[3:0]
units
0101
0111
1000
1001
1010
1011
MCLK/64
MCLK/128
MCLK/256
MCLK/512
MCLK/1024
MCLK/2048
Table 1. Operating Clock Control Register
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