參數(shù)資料
型號(hào)： HV7121B
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： CMOS IMAGE SENSOR With 8-bit ADC
中文描述： SPECIALTY ANALOG CIRCUIT, CQCC48
封裝： CERAMIC, LCC-48
文件頁(yè)數(shù)： 13/30頁(yè)
文件大?。?/td> 446K
代理商： HV7121B
HV7121B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 13 1999 Hyundai System IC
Division
Bit
00
01
10
11
Output data type
Data level - Reference level
Reference level
Data level
Reserved
n
Mode B[3] :
hs_out
(HSYNC output configuration) <
default value : 0b>
This bit offers two types output style about HSYNC signal. HSYNC only mode and HSYNC & internal
clock mode. If the
hs_out
is set to one, HSYNC output signal is ANDed signal of internal pixel clock
and data valid. Otherwise HSYNC output pin keep data high state during valid output period. When
HSYNC & internal clock mode is set, HSYNC output can be used as a pixel data output clock.
data valid
MUX HSYNC
pixel clock
Mode B[3]
n
Mode B[2] :
scr_size
(screen size select) <
default value : 1b>
Flexible screen size is very useful for customer. If the
scr_size
is set to high, i.e. window mode, only
pixels in windowed area defined by register 10h ~ 17h can be read . But
scr_size
is set to low state, i.e.
full screen mode, all pixels in the sensor are read out regardless the values of register 10h ~ 17h. We
can select window mode or full screen mode with this bit. Full screen size is only for chip test.
- window start point :
x : row start address (register 10h, 11h)
y : column start address (register 12h, 13h)
- window end point :
x : row start address + window width address (register 14h, 15h) - 1
y : column start address + window height address (register 16h, 17h) -1
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