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參數(shù)資料
| 型號： | HV7121B |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | CMOS IMAGE SENSOR With 8-bit ADC |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數(shù)： | 25/30頁 |
| 文件大?。?/td> | 446K |
| 代理商： | HV7121B |
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HV7121B
Electronics Industries Co., Ltd.
System IC Division
CMOS IMAGE SENSOR
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA41990615R_1.0 25 1999 Hyundai System IC
Division
(2) Frame Timing Diagram for Integration Time > (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows
RowStartAddress = 6; WindowHeight = 302;
ColumnStartAddress = 6; WindowWidth = 402;
IntegrationTime = 600 [Line Mode];
EffectiveWindowHeight is “302” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e. 314 > (6
+ 302 + 1), is met, and Scale is “1” for integration time is line mode. Therefore, (Integration Time <
EffectiveWindowHeight * Scale), i.e. 600 > 302 * 1, is met, and Idle Slot of Line Mode, i.e. (600 - 302) * 1024
clocks idle slot, is inserted before the next frame initiation.
Overall Frames Sequence
MCLK
ENB
VSYNC
Delay
Slots
Fig. 5 Initial Data Setup Time after ENB gets active
ENB
Deglitch
2 clocks
Sensor Reset
SensorArrayHeight clocks
[314 clocks]
One Line Time Delay
(SensorArrayWidth +
HBLANK) clocks
[417 clocks]
VSYNC
3 clocks
Integration Time * Scale
clocks
[600 * 414 clocks]
I
L
L
L
....
L
L
L
....
L
L
L
....
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HV7121B-COB | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:CMOS IMAGE SENSOR With 8-bit ADC |
| HV7121B-COF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:CMOS IMAGE SENSOR With 8-bit ADC |
| HV7121GP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sensor |
| HV712PG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| HV712X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
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